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riscv-gcc-1
Commit 8ac658b6 by Richard Zidlicky Committed by Bernardo Innocenti
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m68k.md: Fix constraints for bitfield instructions. 

2004-03-16   Richard Zidlicky  <rz@linux-m68k.org>

	* config/m68k/m68k.md: Fix constraints for bitfield instructions.
	* doc/md.texi: Clarify description of "i" constraint.

From-SVN: r79523
parent 1a478672
Showing with 30 additions and 25 deletions
gcc/ChangeLog
2004-03-16 Richard Zidlicky <rz@linux-m68k.org>
* config/m68k/m68k.md: Fix constraints for bitfield instructions.
* doc/md.texi: Clarify description of "i" constraint.
2004-03-15 James E Wilson <wilson@specifixinc.com>
* config/mips/mips.md (type): Split load into load, fpload, fpidxload.
......
gcc/config/m68k/m68k.md
......@@ -4737,8 +4737,8 @@
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
(match_operand:SI 2 "general_operand" "dn")
(match_operand:SI 3 "general_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
......@@ -4753,8 +4753,8 @@
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
(zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
(match_operand:SI 2 "general_operand" "di,di")
(match_operand:SI 3 "general_operand" "di,di")))]
(match_operand:SI 2 "general_operand" "dn,dn")
(match_operand:SI 3 "general_operand" "dn,dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (GET_CODE (operands[2]) == CONST_INT)
......@@ -4771,8 +4771,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
(match_operand 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
......@@ -4786,8 +4786,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
{
......@@ -4797,8 +4797,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
{
......@@ -4816,8 +4816,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,%0{%b2:%b1}")
......@@ -4828,16 +4828,16 @@
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
(match_operand:SI 2 "general_operand" "dn")
(match_operand:SI 3 "general_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
(match_operand:SI 2 "general_operand" "dn")
(match_operand:SI 3 "general_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (GET_CODE (operands[2]) == CONST_INT)
......@@ -4854,8 +4854,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
{
......@@ -4865,8 +4865,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
{
......@@ -4876,8 +4876,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
{
......@@ -4899,7 +4899,7 @@
[(set (cc0)
(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "general_operand" "di")))]
(match_operand:SI 2 "general_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (operands[1] == const1_rtx
......@@ -4924,7 +4924,7 @@
[(set (cc0)
(zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "general_operand" "di")))]
(match_operand:SI 2 "general_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (operands[1] == const1_rtx
......
gcc/doc/md.texi
......@@ -800,7 +800,7 @@ register.
@item @samp{i}
An immediate integer operand (one with constant value) is allowed.
This includes symbolic constants whose values will be known only at
assembly time.
assembly time or later.
@cindex @samp{n} in constraint
@item @samp{n}
......
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