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Commit 8a498f99 by Chung-Ju Wu Committed by Chung-Ju Wu
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Refine formatting and comments. 

gcc/
	* config/nds32/nds32.c: Refine formatting and comments.
	* config/nds32/nds32.h: Likewise.
	* config/nds32/nds32.md: Likewise.
	* config/nds32/nds32-cost.c: Likewise.
	* config/nds32/nds32-isr.c: Likewise.
	* config/nds32/nds32-md-auxiliary.c: Likewise.
	* config/nds32/nds32-multiple.md: Likewise.
	* config/nds32/nds32-predicates.c: Likewise.

From-SVN: r252874
parent ebc6a85e
Showing with 152 additions and 141 deletions
gcc/ChangeLog
2017-09-16 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.c: Refine formatting and comments.
* config/nds32/nds32.h: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32-cost.c: Likewise.
* config/nds32/nds32-isr.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
2017-09-15 Andrew Sutton <andrew.n.sutton@gmail.com>
Jakub Jelinek <jakub@redhat.com>
......
gcc/config/nds32/nds32-cost.c
......@@ -99,7 +99,7 @@ size_cost:
{
case SET:
/* For 'SET' rtx, we need to return false
so that it can recursively calculate costs. */
so that it can recursively calculate costs. */
return false;
case USE:
......@@ -109,7 +109,7 @@ size_cost:
case CONST_INT:
/* All instructions involving constant operation
need to be considered for cost evaluation. */
need to be considered for cost evaluation. */
if (outer_code == SET)
{
/* (set X imm5s), use movi55, 2-byte cost.
......@@ -202,17 +202,17 @@ size_cost:
case POST_INC:
case POST_DEC:
/* We encourage that rtx contains
POST_MODIFY/POST_INC/POST_DEC behavior. */
POST_MODIFY/POST_INC/POST_DEC behavior. */
return 0;
case SYMBOL_REF:
/* We can have gp-relative load/store for symbol_ref.
Have it 4-byte cost. */
Have it 4-byte cost. */
return COSTS_N_INSNS (1);
case CONST:
/* It is supposed to be the pattern (const (plus symbol_ref const_int)).
Have it 4-byte cost. */
Have it 4-byte cost. */
return COSTS_N_INSNS (1);
case REG:
......@@ -221,14 +221,14 @@ size_cost:
case PLUS:
/* We do not need to check if the address is a legitimate address,
because this hook is never called with an invalid address.
But we better check the range of
const_int value for cost, if it exists. */
because this hook is never called with an invalid address.
But we better check the range of
const_int value for cost, if it exists. */
plus0 = XEXP (address, 0);
plus1 = XEXP (address, 1);
if (REG_P (plus0) && CONST_INT_P (plus1))
{
{
/* If it is possible to be lwi333/swi333 form,
make it 2-byte cost. */
if (satisfies_constraint_Iu05 (plus1))
......
gcc/config/nds32/nds32-isr.c
......@@ -171,20 +171,20 @@ nds32_emit_isr_vector_section (int vector_id)
if (nds32_isr_vector_size == 4)
{
/* This block is for 4-byte vector size.
Hardware $VID support is necessary and only one instruction
is needed in vector section. */
Hardware $VID support is necessary and only one instruction
is needed in vector section. */
fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
first_level_handler_name);
}
else
{
/* This block is for 16-byte vector size.
There is NO hardware $VID so that we need several instructions
such as pushing GPRs and preparing software vid at vector section.
For pushing GPRs, there are four variations for
16-byte vector content and we have to handle each combination.
For preparing software vid, note that the vid need to
be substracted vector_number_offset. */
There is NO hardware $VID so that we need several instructions
such as pushing GPRs and preparing software vid at vector section.
For pushing GPRs, there are four variations for
16-byte vector content and we have to handle each combination.
For preparing software vid, note that the vid need to
be substracted vector_number_offset. */
if (TARGET_REDUCED_REGS)
{
if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
......@@ -449,12 +449,12 @@ nds32_construct_isr_vectors_information (tree func_attrs,
nds32_isr_vectors[0].category = NDS32_ISR_RESET;
/* Prepare id_list and identify id value so that
we can set total number of vectors. */
we can set total number of vectors. */
id_list = TREE_VALUE (reset);
id = TREE_VALUE (id_list);
/* The total vectors = interrupt + exception numbers + reset.
There are 8 exception and 1 reset in nds32 architecture. */
There are 8 exception and 1 reset in nds32 architecture. */
nds32_isr_vectors[0].total_n_vectors = TREE_INT_CST_LOW (id) + 8 + 1;
strcpy (nds32_isr_vectors[0].func_name, func_name);
......
gcc/config/nds32/nds32-md-auxiliary.c
......@@ -453,33 +453,33 @@ nds32_output_32bit_load_s (rtx *operands, int byte)
{
case REG:
/* (mem (reg X))
=> access location by using register,
use "lbsi / lhsi" */
=> access location by using register,
use "lbsi / lhsi" */
snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
break;
case SYMBOL_REF:
case CONST:
/* (mem (symbol_ref X))
(mem (const (...)))
=> access global variables,
use "lbsi.gp / lhsi.gp" */
(mem (const (...)))
=> access global variables,
use "lbsi.gp / lhsi.gp" */
operands[1] = XEXP (operands[1], 0);
snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
break;
case POST_INC:
/* (mem (post_inc reg))
=> access location by using register which will be post increment,
use "lbsi.bi / lhsi.bi" */
=> access location by using register which will be post increment,
use "lbsi.bi / lhsi.bi" */
snprintf (pattern, sizeof (pattern),
"l%csi.bi\t%%0, %%1, %d", size, byte);
break;
case POST_DEC:
/* (mem (post_dec reg))
=> access location by using register which will be post decrement,
use "lbsi.bi / lhsi.bi" */
=> access location by using register which will be post decrement,
use "lbsi.bi / lhsi.bi" */
snprintf (pattern, sizeof (pattern),
"l%csi.bi\t%%0, %%1, -%d", size, byte);
break;
......@@ -585,8 +585,8 @@ nds32_output_stack_push (rtx par_rtx)
&& (cfun->machine->va_args_size == 0))
{
/* For stack v3push:
operands[0]: Re
operands[1]: imm8u */
operands[0]: Re
operands[1]: imm8u */
/* This variable is to check if 'push25 Re,imm8u' is available. */
int sp_adjust;
......@@ -595,7 +595,7 @@ nds32_output_stack_push (rtx par_rtx)
operands[0] = gen_rtx_REG (SImode, re_callee_saved);
/* Check if we can generate 'push25 Re,imm8u',
otherwise, generate 'push25 Re,0'. */
otherwise, generate 'push25 Re,0'. */
sp_adjust = cfun->machine->local_size
+ cfun->machine->out_args_size
+ cfun->machine->callee_saved_area_gpr_padding_bytes;
......@@ -611,12 +611,12 @@ nds32_output_stack_push (rtx par_rtx)
else
{
/* For normal stack push multiple:
operands[0]: Rb
operands[1]: Re
operands[2]: En4 */
operands[0]: Rb
operands[1]: Re
operands[2]: En4 */
/* This variable is used to check if we only need to generate En4 field.
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
int push_en4_only_p = 0;
/* Set operands[0] and operands[1]. */
......@@ -678,8 +678,8 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
&& (cfun->machine->va_args_size == 0))
{
/* For stack v3pop:
operands[0]: Re
operands[1]: imm8u */
operands[0]: Re
operands[1]: imm8u */
/* This variable is to check if 'pop25 Re,imm8u' is available. */
int sp_adjust;
......@@ -688,12 +688,12 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
operands[0] = gen_rtx_REG (SImode, re_callee_saved);
/* Check if we can generate 'pop25 Re,imm8u',
otherwise, generate 'pop25 Re,0'.
We have to consider alloca issue as well.
If the function does call alloca(), the stack pointer is not fixed.
In that case, we cannot use 'pop25 Re,imm8u' directly.
We have to caculate stack pointer from frame pointer
and then use 'pop25 Re,0'. */
otherwise, generate 'pop25 Re,0'.
We have to consider alloca issue as well.
If the function does call alloca(), the stack pointer is not fixed.
In that case, we cannot use 'pop25 Re,imm8u' directly.
We have to caculate stack pointer from frame pointer
and then use 'pop25 Re,0'. */
sp_adjust = cfun->machine->local_size
+ cfun->machine->out_args_size
+ cfun->machine->callee_saved_area_gpr_padding_bytes;
......@@ -710,12 +710,12 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
else
{
/* For normal stack pop multiple:
operands[0]: Rb
operands[1]: Re
operands[2]: En4 */
operands[0]: Rb
operands[1]: Re
operands[2]: En4 */
/* This variable is used to check if we only need to generate En4 field.
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
int pop_en4_only_p = 0;
/* Set operands[0] and operands[1]. */
......
gcc/config/nds32/nds32-multiple.md
......@@ -49,9 +49,9 @@
otherwise we have to FAIL this rtx generation:
1. The number of consecutive registers must be integer.
2. Maximum 4 or 8 registers for lmw.bi instruction
(based on this nds32-multiple.md design).
(based on this nds32-multiple.md design).
3. Minimum 2 registers for lmw.bi instruction
(based on this nds32-multiple.md design).
(based on this nds32-multiple.md design).
4. operands[0] must be register for sure.
5. operands[1] must be memory for sure.
6. Do not cross $r15 register because it is not allocatable. */
......@@ -231,9 +231,9 @@
otherwise we have to FAIL this rtx generation:
1. The number of consecutive registers must be integer.
2. Maximum 4 or 8 registers for smw.bi instruction
(based on this nds32-multiple.md design).
(based on this nds32-multiple.md design).
3. Minimum 2 registers for smw.bi instruction
(based on this nds32-multiple.md design).
(based on this nds32-multiple.md design).
4. operands[0] must be memory for sure.
5. operands[1] must be register for sure.
6. Do not cross $r15 register because it is not allocatable. */
......
gcc/config/nds32/nds32-predicates.c
......@@ -175,47 +175,47 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
{
elt = XVECEXP (op, 0, index);
if (GET_CODE (elt) != SET)
return false;
return false;
}
/* For push operation, the parallel rtx looks like:
(parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
(reg:SI Rb))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
(reg:SI Rb+1))
...
(set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
(reg:SI Re))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
(reg:SI FP_REGNUM))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
(reg:SI GP_REGNUM))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
(reg:SI LP_REGNUM))
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int -32)))])
(reg:SI Rb))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
(reg:SI Rb+1))
...
(set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
(reg:SI Re))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
(reg:SI FP_REGNUM))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
(reg:SI GP_REGNUM))
(set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
(reg:SI LP_REGNUM))
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int -32)))])
For pop operation, the parallel rtx looks like:
(parallel [(set (reg:SI Rb)
(mem (reg:SI SP_REGNUM)))
(set (reg:SI Rb+1)
(mem (plus (reg:SI SP_REGNUM) (const_int 4))))
...
(set (reg:SI Re)
(mem (plus (reg:SI SP_REGNUM) (const_int 16))))
(set (reg:SI FP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 20))))
(set (reg:SI GP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 24))))
(set (reg:SI LP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 28))))
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int 32)))]) */
(mem (reg:SI SP_REGNUM)))
(set (reg:SI Rb+1)
(mem (plus (reg:SI SP_REGNUM) (const_int 4))))
...
(set (reg:SI Re)
(mem (plus (reg:SI SP_REGNUM) (const_int 16))))
(set (reg:SI FP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 20))))
(set (reg:SI GP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 24))))
(set (reg:SI LP_REGNUM)
(mem (plus (reg:SI SP_REGNUM) (const_int 28))))
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int 32)))]) */
/* 1. Consecutive registers push/pop operations.
We need to calculate how many registers should be consecutive.
The $sp adjustment rtx, $fp push rtx, $gp push rtx,
and $lp push rtx are excluded. */
We need to calculate how many registers should be consecutive.
The $sp adjustment rtx, $fp push rtx, $gp push rtx,
and $lp push rtx are excluded. */
/* Detect whether we have $fp, $gp, or $lp in the parallel rtx. */
save_fp = reg_mentioned_p (gen_rtx_REG (SImode, FP_REGNUM), op);
......@@ -239,19 +239,19 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
first_regno = REGNO (elt_reg);
/* The 'push' operation is a kind of store operation.
The 'pop' operation is a kind of load operation.
Pass corresponding false/true as second argument (bool load_p).
The par_index is supposed to start with index 0. */
The 'pop' operation is a kind of load operation.
Pass corresponding false/true as second argument (bool load_p).
The par_index is supposed to start with index 0. */
if (!nds32_consecutive_registers_load_store_p (op,
!push_p ? true : false,
0,
first_regno,
rest_count))
return false;
return false;
}
/* 2. Valid $fp/$gp/$lp push/pop operations.
Remember to set start index for checking them. */
Remember to set start index for checking them. */
/* The rest_count is the start index for checking $fp/$gp/$lp. */
index = rest_count;
......@@ -270,9 +270,9 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != FP_REGNUM)
return false;
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != FP_REGNUM)
return false;
}
if (save_gp)
{
......@@ -282,9 +282,9 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != GP_REGNUM)
return false;
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != GP_REGNUM)
return false;
}
if (save_lp)
{
......@@ -294,16 +294,16 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != LP_REGNUM)
return false;
|| GET_CODE (elt_reg) != REG
|| REGNO (elt_reg) != LP_REGNUM)
return false;
}
/* 3. The last element must be stack adjustment rtx.
Its form of rtx should be:
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int X)))
The X could be positive or negative value. */
Its form of rtx should be:
(set (reg:SI SP_REGNUM)
(plus (reg:SI SP_REGNUM) (const_int X)))
The X could be positive or negative value. */
/* Pick up the last element. */
elt = XVECEXP (op, 0, total_count - 1);
......
gcc/config/nds32/nds32.h
......@@ -159,18 +159,18 @@ enum nds32_16bit_address_type
/* This macro is used to return the register number for passing argument.
We need to obey the following rules:
1. If it is required MORE THAN one register,
we need to further check if it really needs to be
aligned on double words.
a) If double word alignment is necessary,
the register number must be even value.
b) Otherwise, the register number can be odd or even value.
we need to further check if it really needs to be
aligned on double words.
a) If double word alignment is necessary,
the register number must be even value.
b) Otherwise, the register number can be odd or even value.
2. If it is required ONLY one register,
the register number can be odd or even value. */
#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
: ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
the register number can be odd or even value. */
#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
: ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
: ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
/* This macro is to check if there are still available registers
......@@ -761,13 +761,13 @@ enum reg_class
The trampoline code for nds32 target must contains following parts:
1. instructions (4 * 4 = 16 bytes):
get $pc first
load chain_value to static chain register via $pc
load nested function address to $r15 via $pc
jump to desired nested function via $r15
get $pc first
load chain_value to static chain register via $pc
load nested function address to $r15 via $pc
jump to desired nested function via $r15
2. data (4 * 2 = 8 bytes):
chain_value
nested function address
chain_value
nested function address
Please check nds32.c implementation for more information. */
#define TRAMPOLINE_SIZE 24
......@@ -906,10 +906,10 @@ enum reg_class
do \
{ \
/* Because our jump table is in text section, \
we need to make sure 2-byte alignment after \
the jump table for instructions fetch. */ \
we need to make sure 2-byte alignment after \
the jump table for instructions fetch. */ \
if (GET_MODE (PATTERN (table)) == QImode) \
ASM_OUTPUT_ALIGN (stream, 1); \
ASM_OUTPUT_ALIGN (stream, 1); \
asm_fprintf (stream, "\t! Jump Table End\n"); \
} while (0)
......
gcc/config/nds32/nds32.md
......@@ -269,12 +269,12 @@
{
case 0:
/* addi Rt4,Rt4,-x ==> subi45 Rt4,x
where 0 <= x <= 31 */
where 0 <= x <= 31 */
operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
return "subi45\t%0, %2";
case 1:
/* addi Rt3,Ra3,-x ==> subi333 Rt3,Ra3,x
where 0 <= x <= 7 */
where 0 <= x <= 7 */
operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
return "subi333\t%0, %1, %2";
case 2:
......@@ -320,7 +320,7 @@
;; and needs to ensure it is exact_log2 value.
(define_insn "*add_slli"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "immediate_operand" " i"))
(match_operand:SI 3 "register_operand" " r")))]
"TARGET_ISA_V3
......@@ -415,9 +415,9 @@
(define_insn "*maddr32_0"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 3 "register_operand" " 0")
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
(plus:SI (match_operand:SI 3 "register_operand" " 0")
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
""
"maddr32\t%0, %1, %2"
[(set_attr "type" "alu")
......@@ -425,9 +425,9 @@
(define_insn "*maddr32_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))
(match_operand:SI 3 "register_operand" " 0")))]
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))
(match_operand:SI 3 "register_operand" " 0")))]
""
"maddr32\t%0, %1, %2"
[(set_attr "type" "alu")
......@@ -435,9 +435,9 @@
(define_insn "*msubr32"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 3 "register_operand" " 0")
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
(minus:SI (match_operand:SI 3 "register_operand" " 0")
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
""
"msubr32\t%0, %1, %2"
[(set_attr "type" "alu")
......@@ -448,10 +448,10 @@
(define_insn "divmodsi4"
[(set (match_operand:SI 0 "register_operand" "=r")
(div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))
(div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))
(set (match_operand:SI 3 "register_operand" "=r")
(mod:SI (match_dup 1) (match_dup 2)))]
(mod:SI (match_dup 1) (match_dup 2)))]
""
"divsr\t%0, %3, %1, %2"
[(set_attr "type" "alu")
......@@ -459,10 +459,10 @@
(define_insn "udivmodsi4"
[(set (match_operand:SI 0 "register_operand" "=r")
(udiv:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))
(udiv:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))
(set (match_operand:SI 3 "register_operand" "=r")
(umod:SI (match_dup 1) (match_dup 2)))]
(umod:SI (match_dup 1) (match_dup 2)))]
""
"divr\t%0, %3, %1, %2"
[(set_attr "type" "alu")
......@@ -2275,8 +2275,8 @@ create_template:
add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
/* If the integer value is not in the range of imm15s,
we need to force register first because our addsi3 pattern
only accept nds32_rimm15s_operand predicate. */
we need to force register first because our addsi3 pattern
only accept nds32_rimm15s_operand predicate. */
add_tmp = force_reg (SImode, add_tmp);
emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
......
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