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riscv-gcc-1
Commit 8a01e7d9 by Naveen.H.S Committed by DJ Delorie
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muldiv.md (umulhisi3_c): Use only registers for dest. 

* config/m32c/muldiv.md (umulhisi3_c): Use only registers for 
dest.
(umulhisi3_r): Likewise.

From-SVN: r115400
parent ec0897de
Showing with 12 additions and 6 deletions
gcc/ChangeLog
2006-07-12 Naveen.H.S <naveenh@kpitcummins.com>
* config/m32c/muldiv.md (umulhisi3_c): Use only registers for
dest.
(umulhisi3_r): Likewise.
2006-07-12 Paolo Carlini <pcarlini@suse.de>
PR libstdc++/27878
......
gcc/config/m32c/muldiv.md
......@@ -107,18 +107,18 @@
)
(define_insn "umulhisi3_c"
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
(match_operand 2 "immediate_operand" "i,i")))]
[(set (match_operand:SI 0 "ra_operand" "=Rsi")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
(match_operand 2 "immediate_operand" "i")))]
""
"mulu.w\t%u2,%1"
[(set_attr "flags" "o")]
)
(define_insn "umulhisi3_r"
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
(zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
[(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
(zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
""
"mulu.w\t%u2,%1"
[(set_attr "flags" "o")]
......
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