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riscv-gcc-1
Commit 89fff9cc by Nicolas Pitre Committed by Richard Earnshaw
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arm - correctly handle denormal results during softfp subtraction 

2018-08-02  Nicolas Pitre <nico@fluxnic.net>

	PR libgcc/86512
	* config/arm/ieee754-df.S (adddf3): Don't shortcut denormal handling
	when exponent goes negative. Update my email address.
	* config/arm/ieee754-sf.S (addsf3): Likewise.

From-SVN: r263267
parent 01557bd4
Showing with 18 additions and 9 deletions
libgcc/ChangeLog
2018-08-02 Nicolas Pitre <nico@fluxnic.net>
PR libgcc/86512
* config/arm/ieee754-df.S: Don't shortcut denormal handling when
exponent goes negative. Update my email address.
* config/arm/ieee754-sf.S: Likewise.
2018-08-01 Martin Liska <mliska@suse.cz> 2018-08-01 Martin Liska <mliska@suse.cz>
* libgcov-profiler.c (__gcov_indirect_call_profiler_v2): Do not * libgcov-profiler.c (__gcov_indirect_call_profiler_v2): Do not
......
libgcc/config/arm/ieee754-df.S
/* ieee754-df.S double-precision floating point support for ARM /* ieee754-df.S double-precision floating point support for ARM
Copyright (C) 2003-2018 Free Software Foundation, Inc. Copyright (C) 2003-2018 Free Software Foundation, Inc.
Contributed by Nicolas Pitre (nico@cam.org) Contributed by Nicolas Pitre (nico@fluxnic.net)
This file is free software; you can redistribute it and/or modify it This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the under the terms of the GNU General Public License as published by the
...@@ -238,9 +238,10 @@ LSYM(Lad_a): ...@@ -238,9 +238,10 @@ LSYM(Lad_a):
movs ip, ip, lsl #1 movs ip, ip, lsl #1
adcs xl, xl, xl adcs xl, xl, xl
adc xh, xh, xh adc xh, xh, xh
tst xh, #0x00100000 subs r4, r4, #1
sub r4, r4, #1 do_it hs
bne LSYM(Lad_e) cmphs xh, #0x00100000
bhs LSYM(Lad_e)
@ No rounding necessary since ip will always be 0 at this point. @ No rounding necessary since ip will always be 0 at this point.
LSYM(Lad_l): LSYM(Lad_l):
......
libgcc/config/arm/ieee754-sf.S
/* ieee754-sf.S single-precision floating point support for ARM /* ieee754-sf.S single-precision floating point support for ARM
Copyright (C) 2003-2018 Free Software Foundation, Inc. Copyright (C) 2003-2018 Free Software Foundation, Inc.
Contributed by Nicolas Pitre (nico@cam.org) Contributed by Nicolas Pitre (nico@fluxnic.net)
This file is free software; you can redistribute it and/or modify it This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the under the terms of the GNU General Public License as published by the
...@@ -168,10 +168,11 @@ LSYM(Lad_e): ...@@ -168,10 +168,11 @@ LSYM(Lad_e):
LSYM(Lad_a): LSYM(Lad_a):
movs r1, r1, lsl #1 movs r1, r1, lsl #1
adc r0, r0, r0 adc r0, r0, r0
tst r0, #0x00800000 subs r2, r2, #1
sub r2, r2, #1 do_it hs
bne LSYM(Lad_e) cmphs r0, #0x00800000
bhs LSYM(Lad_e)
@ No rounding necessary since r1 will always be 0 at this point. @ No rounding necessary since r1 will always be 0 at this point.
LSYM(Lad_l): LSYM(Lad_l):
......
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