Commit 89fdc743 by Ian Bolton Committed by Ian Bolton

AArch64 support for NEG in vector registers for DI and SI mode (part 2)

From-SVN: r201263
parent ee3bf4ae
......@@ -2,6 +2,7 @@
* config/aarch64/aarch64.md (neg<mode>2): Offer alternative that
uses vector registers.
* config/aarch64/iterators.md: Add attributes rtn and vas.
2013-07-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Richard Earnshaw <richard.earnshaw@arm.com>
......
......@@ -283,6 +283,12 @@
(V2DI "") (V2SF "")
(V4SF "") (V2DF "")])
;; Register Type Name and Vector Arrangement Specifier for when
;; we are doing scalar for DI and SIMD for SI (ignoring all but
;; lane 0).
(define_mode_attr rtn [(DI "d") (SI "")])
(define_mode_attr vas [(DI "") (SI ".2s")])
;; Map a floating point mode to the appropriate register name prefix
(define_mode_attr s [(SF "s") (DF "d")])
......
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