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riscv-gcc-1
Commit 893779cc by Nick Clifton Committed by Jeff Law
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thumb.md (extendqisi2_insn): Cope with REG + OFFSET addressing. 

 
        * config/arm/thumb.md (extendqisi2_insn): Cope with REG +
        OFFSET addressing.

From-SVN: r21862
parent bb4c2bf3
Showing with 17 additions and 1 deletions
gcc/config/arm/thumb.md
......@@ -484,7 +484,23 @@
{
ops[1] = XEXP (XEXP (operands[1], 0), 0);
ops[2] = XEXP (XEXP (operands[1], 0), 1);
output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
if (GET_CODE (ops[1]) == REG && GET_CODE (ops[2]) == REG)
output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
else if (GET_CODE (ops[1]) == REG)
{
if (REGNO (ops[1]) == REGNO (operands[0]))
output_asm_insn (\"ldrb\\t%0, [%1, %2]\;lsl\\t%0, %0, #24\;asr\\t%0, %0, #24\", ops);
else
output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
}
else
{
if (REGNO (ops[2]) == REGNO (operands[0]))
output_asm_insn (\"ldrb\\t%0, [%2, %1]\;lsl\\t%0, %0, #24\;asr\\t%0, %0, #24\", ops);
else
output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
}
}
else if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
{
......
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