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riscv-gcc-1
Commit 88b9490b by Uros Bizjak Committed by Uros Bizjak
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i386.md (*btdi_rex64): Change operand 1 predicate to nonmemory_operand. 

	* config/i386/i386.md (*btdi_rex64): Change operand 1 predicate to
	nonmemory_operand. Add "N" operand constraint.
	(*btsi): Ditto.
	(*jcc_btdi_mask_rex64): New instruction and split pattern.
	(*jcc_btsi_mask): Ditto.
	(*jcc_btsi_mask_1): Ditto.

testsuite/ChangeLog:

	* gcc.target/i386/bt-mask-1.c: New test.
	* gcc.target/i386/bt-mask-2.c: Ditto.

From-SVN: r136636
parent 0627bfb4
Showing with 145 additions and 4 deletions
gcc/ChangeLog
2008-06-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*btdi_rex64): Change operand 1 predicate to
nonmemory_operand. Add "N" operand constraint.
(*btsi): Ditto.
(*jcc_btdi_mask_rex64): New instruction and split pattern.
(*jcc_btsi_mask): Ditto.
(*jcc_btsi_mask_1): Ditto.
2008-06-10 Joseph Myers <joseph@codesourcery.com>
* config/rs6000/rs6000.c (build_opaque_vector_type): Set
......
gcc/config/i386/i386.md
......@@ -13819,7 +13819,7 @@
(zero_extract:DI
(match_operand:DI 0 "register_operand" "r")
(const_int 1)
(match_operand:DI 1 "register_operand" "r"))
(match_operand:DI 1 "nonmemory_operand" "rN"))
(const_int 0)))]
"TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
"bt{q}\t{%1, %0|%0, %1}"
......@@ -13831,7 +13831,7 @@
(zero_extract:SI
(match_operand:SI 0 "register_operand" "r")
(const_int 1)
(match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 1 "nonmemory_operand" "rN"))
(const_int 0)))]
"TARGET_USE_BT || optimize_size"
"bt{l}\t{%1, %0|%0, %1}"
......@@ -14117,6 +14117,39 @@
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
;; avoid useless masking of bit offset operand
(define_insn_and_split "*jcc_btdi_mask_rex64"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
[(zero_extract:DI
(match_operand:DI 1 "register_operand" "r")
(const_int 1)
(and:SI
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
(pc)))]
"TARGET_64BIT && (TARGET_USE_BT || optimize_size)
&& (INTVAL (operands[3]) & 0x3f) == 0x3f"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:DI
(match_dup 1)
(const_int 1)
(match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
(label_ref (match_dup 4))
(pc)))]
{
operands[2] = simplify_gen_subreg (DImode, operands[2], SImode, 0);
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
(define_insn_and_split "*jcc_btsi"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
......@@ -14148,6 +14181,35 @@
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
;; avoid useless masking of bit offset operand
(define_insn_and_split "*jcc_btsi_mask"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
[(zero_extract:SI
(match_operand:SI 1 "register_operand" "r")
(const_int 1)
(and:SI
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
(pc)))]
"(TARGET_USE_BT || optimize_size)
&& (INTVAL (operands[3]) & 0x1f) == 0x1f"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:SI
(match_dup 1)
(const_int 1)
(match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
(label_ref (match_dup 4))
(pc)))]
"PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
(define_insn_and_split "*jcc_btsi_1"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
......@@ -14179,6 +14241,39 @@
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
;; avoid useless masking of bit offset operand
(define_insn_and_split "*jcc_btsi_mask_1"
[(set (pc)
(if_then_else
(match_operator 0 "bt_comparison_operator"
[(and:SI
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "r")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")) 0))
(const_int 1))
(const_int 0)])
(label_ref (match_operand 4 "" ""))
(pc)))]
"(TARGET_USE_BT || optimize_size)
&& (INTVAL (operands[3]) & 0x1f) == 0x1f"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:SI
(match_dup 1)
(const_int 1)
(match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
(label_ref (match_dup 4))
(pc)))]
"PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
;; Define combination compare-and-branch fp compare instructions to use
;; during early optimization. Splitting the operation apart early makes
;; for bad code when we want to reverse the operation.
......
gcc/testsuite/ChangeLog
2008-06-10 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/bt-mask-1.c: New test.
* gcc.target/i386/bt-mask-2.c: Ditto.
2008-06-10 Uros Bizjak <ubizjak@gmail.com>
PR target/36473
* testsuite/gcc.target/i386/bt-1.c: New test.
* testsuite/gcc.target/i386/bt-2.c: Ditto.
* gcc.target/i386/bt-1.c: New test.
* gcc.target/i386/bt-2.c: Ditto.
2008-06-09 Andy Hutchinson <hutchinsonandy@aim.com>
......
gcc/testsuite/gcc.target/i386/bt-mask-1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
void foo (void);
int test (int x, int n)
{
n &= 0x1f;
if (x & (0x01 << n))
foo ();
return 0;
}
/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
gcc/testsuite/gcc.target/i386/bt-mask-2.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
void foo (void);
int test (long x, long n)
{
n &= 0x3f;
if (x & ((long)0x01 << n))
foo ();
return 0;
}
/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
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