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Commit 870128f2 by Georg-Johann Lay
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avr.md: Fix indentations of insn C snippets. 

	* config/avr/avr.md: Fix indentations of insn C snippets.

From-SVN: r192136
parent 8f2b580a
Showing with 42 additions and 38 deletions
gcc/ChangeLog
2012-10-05 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md: Fix indentations of insn C snippets.
2012-10-05 Richard Guenther <rguenther@suse.de> 2012-10-05 Richard Guenther <rguenther@suse.de>
PR middle-end/54811 PR middle-end/54811
...@@ -4335,7 +4339,7 @@ ...@@ -4335,7 +4339,7 @@
2012-08-17 Nick Clifton <nickc@redhat.com> 2012-08-17 Nick Clifton <nickc@redhat.com>
* config/fr30/fr30.md (cbranchsi4): Remove mode from comparison. * config/fr30/fr30.md (cbranchsi4): Remove mode from comparison.
(branch_true): Likewise. (branch_true): Likewise.
(branch_false): Likewise. (branch_false): Likewise.
...@@ -17959,7 +17963,7 @@ ...@@ -17959,7 +17963,7 @@
* config/arm/linux-eabi.h (GLIBC_DYNAMIC_LINKER_SOFT_FLOAT): Define. * config/arm/linux-eabi.h (GLIBC_DYNAMIC_LINKER_SOFT_FLOAT): Define.
(GLIBC_DYNAMIC_LINKER_HARD_FLOAT): Define. (GLIBC_DYNAMIC_LINKER_HARD_FLOAT): Define.
(GLIBC_DYNAMIC_LINKER_DEFAULT): Define. (GLIBC_DYNAMIC_LINKER_DEFAULT): Define.
(GLIBC_DYNAMIC_LINKER): Redefine to use the hard float path. (GLIBC_DYNAMIC_LINKER): Redefine to use the hard float path.
2012-04-25 Sriraman Tallam <tmsriram@google.com> 2012-04-25 Sriraman Tallam <tmsriram@google.com>
......
gcc/config/avr/avr.md
...@@ -4167,13 +4167,13 @@ ...@@ -4167,13 +4167,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (QImode, HImode); unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
unsigned int high_off = subreg_highpart_offset (QImode, HImode); unsigned int high_off = subreg_highpart_offset (QImode, HImode);
operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off); operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off); operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
}) })
(define_insn_and_split "zero_extendqipsi2" (define_insn_and_split "zero_extendqipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r") [(set (match_operand:PSI 0 "register_operand" "=r")
...@@ -4198,13 +4198,13 @@ ...@@ -4198,13 +4198,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (zero_extend:HI (match_dup 1))) [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (HImode, SImode); unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
unsigned int high_off = subreg_highpart_offset (HImode, SImode); unsigned int high_off = subreg_highpart_offset (HImode, SImode);
operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
}) })
(define_insn_and_split "zero_extendhipsi2" (define_insn_and_split "zero_extendhipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r") [(set (match_operand:PSI 0 "register_operand" "=r")
...@@ -4248,13 +4248,13 @@ ...@@ -4248,13 +4248,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (HImode, SImode); unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
unsigned int high_off = subreg_highpart_offset (HImode, SImode); unsigned int high_off = subreg_highpart_offset (HImode, SImode);
operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
}) })
(define_insn_and_split "zero_extendpsisi2" (define_insn_and_split "zero_extendpsisi2"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -4277,13 +4277,13 @@ ...@@ -4277,13 +4277,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (zero_extend:SI (match_dup 1))) [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (SImode, DImode); unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
unsigned int high_off = subreg_highpart_offset (SImode, DImode); unsigned int high_off = subreg_highpart_offset (SImode, DImode);
operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
}) })
(define_insn_and_split "zero_extendhidi2" (define_insn_and_split "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -4293,13 +4293,13 @@ ...@@ -4293,13 +4293,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (zero_extend:SI (match_dup 1))) [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (SImode, DImode); unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
unsigned int high_off = subreg_highpart_offset (SImode, DImode); unsigned int high_off = subreg_highpart_offset (SImode, DImode);
operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
}) })
(define_insn_and_split "zero_extendsidi2" (define_insn_and_split "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -4309,13 +4309,13 @@ ...@@ -4309,13 +4309,13 @@
"reload_completed" "reload_completed"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 3) (const_int 0))] (set (match_dup 3) (const_int 0))]
{ {
unsigned int low_off = subreg_lowpart_offset (SImode, DImode); unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
unsigned int high_off = subreg_highpart_offset (SImode, DImode); unsigned int high_off = subreg_highpart_offset (SImode, DImode);
operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
}) })
;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
;; compare ;; compare
......
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