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riscv-gcc-1
Commit 8695f61e by Steven Bosscher
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k6.md: Rewrite using the DFA model. 

	* config/i386/k6.md: Rewrite using the DFA model.
	* config/i386/i386.c (ix86_adjust_cost): Don't increase the
	cost of load-operation insns for the K6.
	(ia32_use_dfa_pipeline_interface): Add TARGET_K6.
	(ia32_multipass_dfa_lookahead): Likewise.

From-SVN: r82859
parent 28245018
Showing with 22 additions and 18 deletions
gcc/ChangeLog
2004-06-09 Steven Bosscher <stevenb@suse.de>
* config/i386/k6.md: Rewrite using the DFA model.
* config/i386/i386.c (ix86_adjust_cost): Don't increase the
cost of load-operation insns for the K6.
(ia32_use_dfa_pipeline_interface): Add TARGET_K6.
(ia32_multipass_dfa_lookahead): Likewise.
2004-06-09 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.c (alpha_gimplify_va_arg_1,
......@@ -131,8 +139,8 @@
2004-06-08 Jeff Law <law@redhat.com>
* doc/contrib.texi: Add entries for Stefan Olsson and
Ola Ronnerup.
* doc/contrib.texi: Add entries for Stefan Olsson and
Ola Ronnerup.
2004-06-08 DJ Delorie <dj@redhat.com>
......@@ -155,13 +163,13 @@
2004-06-08 Richard Henderson <rth@redhat.com>
* gimple-low.c (struct lower_data): Replace the_return_label and
one_return_stmt with return_statements.
(lower_function_body): Process the entire list of return_statements.
(lower_return_expr): Check source value before unifying return_exprs.
* gimplify.c (gimplify_return_expr): Force the use of a temporary
for !aggregate_value_p.
* tree-gimple.c: Update RETURN_EXPR grammer.
* gimple-low.c (struct lower_data): Replace the_return_label and
one_return_stmt with return_statements.
(lower_function_body): Process the entire list of return_statements.
(lower_return_expr): Check source value before unifying return_exprs.
* gimplify.c (gimplify_return_expr): Force the use of a temporary
for !aggregate_value_p.
* tree-gimple.c: Update RETURN_EXPR grammer.
2004-06-08 Vladimir Makarov <vmakarov@redhat.com>
......
gcc/config/i386/i386.c
......@@ -12482,7 +12482,7 @@ static int
ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
{
enum attr_type insn_type, dep_insn_type;
enum attr_memory memory, dep_memory;
enum attr_memory memory;
rtx set, set2;
int dep_insn_code_number;
......@@ -12550,18 +12550,13 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case PROCESSOR_K6:
memory = get_attr_memory (insn);
dep_memory = get_attr_memory (dep_insn);
/* The esp dependency is resolved before the instruction is really
finished. */
if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
return 1;
/* Since we can't represent delayed latencies of load+operation,
increase the cost here for non-imov insns. */
if (dep_memory == MEMORY_LOAD || dep_memory == MEMORY_BOTH)
cost += (dep_insn_type != TYPE_IMOV) ? 2 : 1;
/* INT->FP conversion is expensive. */
if (get_attr_fp_int_src (dep_insn))
cost += 5;
......@@ -12587,7 +12582,6 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
memory = get_attr_memory (insn);
dep_memory = get_attr_memory (dep_insn);
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
......@@ -12626,6 +12620,7 @@ ia32_use_dfa_pipeline_interface (void)
{
if (TARGET_PENTIUM
|| TARGET_PENTIUMPRO
|| TARGET_K6
|| TARGET_ATHLON_K8)
return 1;
return 0;
......@@ -12641,7 +12636,8 @@ ia32_multipass_dfa_lookahead (void)
if (ix86_tune == PROCESSOR_PENTIUM)
return 2;
if (ix86_tune == PROCESSOR_PENTIUMPRO)
if (ix86_tune == PROCESSOR_PENTIUMPRO
|| ix86_tune == PROCESSOR_K6)
return 1;
else
......
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