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Commit 8691cea3 by Uros Bizjak Committed by Uros Bizjak
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re PR target/31019 (Microoptimization of the i386 and x86_64 compilers) 

	PR target/31019
	* config/i386/i386.h (TUNEMASK): Redefine to use ix86_tune_mask.
	(ARCHMASK): Define.
	(TARGET_CMOVE): Use ARCHMASK.
	(TARGET_CMPXCHG): Ditto.
	(TARGET_CMPXCHG8B): Ditto.
	(TARGET_XADD): Ditto.
	(TARGET_BSWAP): Ditto.
	* config/i386/i386.c (ix86_tune_mask): New global variable.
	(ix86_arch_mask): Ditto.
	(override_options): Initialize ix86_tune_mask and
	ix86_arch_mask. Use ARCHMASK to clear MASK_NO_FANCY_MATH_387 in
	target_flags.


Co-Authored-By: Michael Meissner <michael.meissner@amd.com>

From-SVN: r122473
parent 4e223867
Showing with 43 additions and 14 deletions
gcc/ChangeLog
2007-03-02 Uros Bizjak <ubizjak@gmail.com>
Michael Meissner <michael.meissner@amd.com>
PR target/31019
* config/i386/i386.h (TUNEMASK): Redefine to use ix86_tune_mask.
(ARCHMASK): Define.
(TARGET_CMOVE): Use ARCHMASK.
(TARGET_CMPXCHG): Ditto.
(TARGET_CMPXCHG8B): Ditto.
(TARGET_XADD): Ditto.
(TARGET_BSWAP): Ditto.
* config/i386/i386.c (ix86_tune_mask): New global variable.
(ix86_arch_mask): Ditto.
(override_options): Initialize ix86_tune_mask and
ix86_arch_mask. Use ARCHMASK to clear MASK_NO_FANCY_MATH_387 in
target_flags.
2007-03-02 Ben Elliston <bje@au.ibm.com>
PR 30992
......
gcc/config/i386/i386.c
......@@ -984,23 +984,25 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_486 (1<<PROCESSOR_I486)
#define m_PENT (1<<PROCESSOR_PENTIUM)
#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
#define m_NOCONA (1<<PROCESSOR_NOCONA)
#define m_CORE2 (1<<PROCESSOR_CORE2)
#define m_GEODE (1<<PROCESSOR_GEODE)
#define m_K6_GEODE (m_K6 | m_GEODE)
#define m_K6 (1<<PROCESSOR_K6)
#define m_ATHLON (1<<PROCESSOR_ATHLON)
#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
#define m_K6_GEODE (m_K6 | m_GEODE)
#define m_K8 (1<<PROCESSOR_K8)
#define m_ATHLON (1<<PROCESSOR_ATHLON)
#define m_ATHLON_K8 (m_K8 | m_ATHLON)
#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
#define m_NOCONA (1<<PROCESSOR_NOCONA)
#define m_CORE2 (1<<PROCESSOR_CORE2)
#define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
#define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
/* Generic instruction choice should be common subset of supported CPUs
(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
Generic64 seems like good code size tradeoff. We can't enable it for 32bit
......@@ -1395,8 +1397,11 @@ enum fpmath_unit ix86_fpmath;
/* Which cpu are we scheduling for. */
enum processor_type ix86_tune;
int ix86_tune_mask;
/* Which instruction set architecture to use. */
enum processor_type ix86_arch;
int ix86_arch_mask;
/* true if sse prefetch instruction is not NOOP. */
int x86_prefetch_sse;
......@@ -2074,8 +2079,10 @@ override_options (void)
if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
{
ix86_arch = processor_alias_table[i].processor;
ix86_arch_mask = 1 << ix86_arch;
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
ix86_tune_mask = 1 << ix86_tune;
if (processor_alias_table[i].flags & PTA_MMX
&& !(target_flags_explicit & MASK_MMX))
target_flags |= MASK_MMX;
......@@ -2276,7 +2283,7 @@ override_options (void)
/* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
since the insns won't need emulation. */
if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
if (x86_arch_always_fancy_math_387 & ARCHMASK)
target_flags &= ~MASK_NO_FANCY_MATH_387;
/* Likewise, if the target doesn't have a 387, or we've specified
......
gcc/config/i386/i386.h
......@@ -179,7 +179,6 @@ extern const struct processor_costs *ix86_cost;
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TUNEMASK (1 << ix86_tune)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
extern const int x86_branch_hints, x86_unroll_strlen;
......@@ -208,6 +207,9 @@ extern const int x86_bswap;
extern const int x86_partial_flag_reg_stall;
extern int x86_prefetch_sse, x86_cmpxchg16b;
#define TUNEMASK ix86_tune_mask
#define ARCHMASK ix86_arch_mask
#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
......@@ -215,7 +217,7 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
/* For sane SSE instruction set generation we need fcomi instruction. It is
safe to enable all CMOVE instructions. */
#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
#define TARGET_CMOVE ((x86_cmove & ARCHMASK) || TARGET_SSE)
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
......@@ -276,11 +278,11 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
#define TARGET_CMPXCHG (x86_cmpxchg & ARCHMASK)
#define TARGET_CMPXCHG8B (x86_cmpxchg8b & ARCHMASK)
#define TARGET_CMPXCHG16B (x86_cmpxchg16b)
#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
#define TARGET_BSWAP (x86_bswap & (1 << ix86_arch))
#define TARGET_XADD (x86_xadd & ARCHMASK)
#define TARGET_BSWAP (x86_bswap & ARCHMASK)
#ifndef TARGET_64BIT_DEFAULT
#define TARGET_64BIT_DEFAULT 0
......@@ -2130,7 +2132,10 @@ enum processor_type
};
extern enum processor_type ix86_tune;
extern int ix86_tune_mask;
extern enum processor_type ix86_arch;
extern int ix86_arch_mask;
enum fpmath_unit
{
......
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