Commit 862bff88 by Jeff Law

mn10300.c (expand_epilogue): Correctly handle functions with large frames, but…

mn10300.c (expand_epilogue): Correctly handle functions with large frames, but no callee register saves.

        * mn10300/mn10300.c (expand_epilogue): Correctly handle functions
        with large frames, but no callee register saves.

        * mn10300/mn1300.md (movdf, movdi): Handle overlapping moves.

From-SVN: r13757
parent 90304f64
...@@ -183,18 +183,47 @@ ...@@ -183,18 +183,47 @@
(match_operand:DI 1 "general_operand" "0,0,I,d,a,d,a,dim,aim,dim,aim"))] (match_operand:DI 1 "general_operand" "0,0,I,d,a,d,a,dim,aim,dim,aim"))]
"register_operand (operands[0], DImode) "register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)" || register_operand (operands[1], DImode)"
"@ "*
nop {
nop switch (which_alternative)
clr %L0\;clr %H0 {
mov %L1,%L0\;mov %H1,%H0 case 0:
mov %L1,%L0\;mov %H1,%H0 case 1:
mov %L1,%L0\;mov %H1,%H0 return \"nop\";
mov %L1,%L0\;mov %H1,%H0
mov %L1,%L0\;mov %H1,%H0 case 2:
mov %L1,%L0\;mov %H1,%H0 return \"clr %L0\;clr %H0\";
mov %L1,%L0\;mov %H1,%H0
mov %L1,%L0\;mov %H1,%H0" case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
if (GET_CODE (operands[1]) == MEM
&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
{
rtx temp = operands[0];
while (GET_CODE (temp) == SUBREG)
temp = SUBREG_REG (temp);
if (GET_CODE (temp) != REG)
abort ();
if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
XEXP (operands[1], 0)))
return \"mov %H1,%H0\;mov %L1,%L0\";
else
return \"mov %L1,%L0\;mov %H1,%H0\";
}
else
return \"mov %L1,%L0\;mov %H1,%H0\";
}
}"
[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
(define_expand "movdf" (define_expand "movdf"
...@@ -214,18 +243,47 @@ ...@@ -214,18 +243,47 @@
(match_operand:DF 1 "general_operand" "0,0,G,d,a,d,a,dim,aim,dim,aim"))] (match_operand:DF 1 "general_operand" "0,0,G,d,a,d,a,dim,aim,dim,aim"))]
"register_operand (operands[0], DFmode) "register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode)" || register_operand (operands[1], DFmode)"
"@ "*
nop {
nop switch (which_alternative)
clr %L0\;clr %H0 {
mov %L1,%L0\;mov %H1,%H0 case 0:
mov %L1,%L0\;mov %H1,%H0 case 1:
mov %L1,%L0\;mov %H1,%H0 return \"nop\";
mov %L1,%L0\;mov %H1,%H0
mov %L1,%L0\;mov %H1,%H0 case 2:
mov %L1,%L0\;mov %H1,%H0 return \"clr %L0\;clr %H0\";
mov %L1,%L0\;mov %H1,%H0
mov %L1,%L0\;mov %H1,%H0" case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
if (GET_CODE (operands[1]) == MEM
&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
{
rtx temp = operands[0];
while (GET_CODE (temp) == SUBREG)
temp = SUBREG_REG (temp);
if (GET_CODE (temp) != REG)
abort ();
if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
XEXP (operands[1], 0)))
return \"mov %H1,%H0\;mov %L1,%L0\";
else
return \"mov %L1,%L0\;mov %H1,%H0\";
}
else
return \"mov %L1,%L0\;mov %H1,%H0\";
}
}"
[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")]) [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
......
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