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Commit 85d9c13c by Trevor Smigiel
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configure.in (skipdirs): Don't build target-libiberty for SPU. 

ChangeLog

	* configure.in (skipdirs) : Don't build target-libiberty for SPU.
	* configure : Rebuilt.

gcc/ChangeLog

	* config.gcc : Add target for SPU.
	* config/spu/constraints.md : New file.
	* config/spu/crt0.c : New file.
	* config/spu/crtend.c : New file.
	* config/spu/crti.asm : New file.
	* config/spu/crtn.asm : New file.
	* config/spu/float_unsdidf.c : New file.
	* config/spu/float_unssidf.c : New file.
	* config/spu/predicates.md : New file.
	* config/spu/spu-builtins.def : New file.
	* config/spu/spu-builtins.h : New file.
	* config/spu/spu-builtins.md : New file.
	* config/spu/spu-c.c : New file.
	* config/spu/spu-elf.h : New file.
	* config/spu/spu-modes.def : New file.
	* config/spu/spu-protos.h : New file.
	* config/spu/spu.c : New file.
	* config/spu/spu.h : New file.
	* config/spu/spu.md : New file.
	* config/spu/spu.opt : New file.
	* config/spu/spu_internals.h : New file.
	* config/spu/spu_intrinsics.h : New file.
	* config/spu/spu_mfcio.h : New file.
	* config/spu/t-spu-elf : New file.
	* config/spu/vec_types.h : New file.
	* config/spu/vmx2spu.h : New file.
	* doc/contrib.texi : Document SPU contributor.
	* doc/extend.texi : Document SPU extensions.
	* doc/invoke.texi : Document SPU options.
	* doc/md.texi : Document SPU constraints.

libcpp/ChangeLog

	* configure.ac (need_64bit_hwint): Need 64bit hwint for SPU.
	* configure : Rebuilt.

From-SVN: r119041
parent 99f8a411
Showing with 1459 additions and 2 deletions
ChangeLog
2006-11-20 Trevor Smigiel <trevor_smigiel@playstation.sony.com> 2006-11-20 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
* configure.in (skipdirs) : Don't build target-libiberty for SPU.
* configure : Rebuilt.
2006-11-20 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
* MAINTAINERS (Write After Approval): Add myself. * MAINTAINERS (Write After Approval): Add myself.
2006-11-20 Andrea Ornstein <andrea.ornstein@st.com> 2006-11-20 Andrea Ornstein <andrea.ornstein@st.com>
......
configure
...@@ -1598,6 +1598,9 @@ case "${target}" in ...@@ -1598,6 +1598,9 @@ case "${target}" in
;; ;;
sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*) sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
;; ;;
spu-*-*)
skipdirs="target-libiberty"
;;
v810-*-*) v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}" noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;; ;;
......
configure.in
...@@ -774,6 +774,9 @@ case "${target}" in ...@@ -774,6 +774,9 @@ case "${target}" in
;; ;;
sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*) sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
;; ;;
spu-*-*)
skipdirs="target-libiberty"
;;
v810-*-*) v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}" noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;; ;;
......
gcc/ChangeLog
2006-11-20 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
Russell Olsen <Russell_Olsen@playstation.sony.com>
Dmitri Makarov <Dmitri_Makarov@playstation.sony.com>
Yukishige Shibata <shibata@rd.scei.sony.co.jp>
Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
Andrew Pinski <Andrew_Pinski@playstation.sony.com>
* config.gcc : Add target for SPU.
* config/spu/constraints.md : New file.
* config/spu/crt0.c : New file.
* config/spu/crtend.c : New file.
* config/spu/crti.asm : New file.
* config/spu/crtn.asm : New file.
* config/spu/float_unsdidf.c : New file.
* config/spu/float_unssidf.c : New file.
* config/spu/predicates.md : New file.
* config/spu/spu-builtins.def : New file.
* config/spu/spu-builtins.h : New file.
* config/spu/spu-builtins.md : New file.
* config/spu/spu-c.c : New file.
* config/spu/spu-elf.h : New file.
* config/spu/spu-modes.def : New file.
* config/spu/spu-protos.h : New file.
* config/spu/spu.c : New file.
* config/spu/spu.h : New file.
* config/spu/spu.md : New file.
* config/spu/spu.opt : New file.
* config/spu/spu_internals.h : New file.
* config/spu/spu_intrinsics.h : New file.
* config/spu/spu_mfcio.h : New file.
* config/spu/t-spu-elf : New file.
* config/spu/vec_types.h : New file.
* config/spu/vmx2spu.h : New file.
* doc/contrib.texi : Document SPU contributor.
* doc/extend.texi : Document SPU extensions.
* doc/invoke.texi : Document SPU options.
* doc/md.texi : Document SPU constraints.
2006-11-21 Zdenek Dvorak <dvorakz@suse.cz> 2006-11-21 Zdenek Dvorak <dvorakz@suse.cz>
* cfgloopmanip.c (add_loop, duplicate_loop): Do not set level * cfgloopmanip.c (add_loop, duplicate_loop): Do not set level
......
gcc/config.gcc
...@@ -321,6 +321,10 @@ sparc64*-*-*) ...@@ -321,6 +321,10 @@ sparc64*-*-*)
sparc*-*-*) sparc*-*-*)
cpu_type=sparc cpu_type=sparc
;; ;;
spu*-*-*)
cpu_type=spu
need_64bit_hwint=yes
;;
s390*-*-*) s390*-*-*)
cpu_type=s390 cpu_type=s390
need_64bit_hwint=yes need_64bit_hwint=yes
...@@ -2326,6 +2330,14 @@ sparc64-*-netbsd*) ...@@ -2326,6 +2330,14 @@ sparc64-*-netbsd*)
extra_options="${extra_options} sparc/long-double-switch.opt" extra_options="${extra_options} sparc/long-double-switch.opt"
tmake_file="${tmake_file} sparc/t-netbsd64" tmake_file="${tmake_file} sparc/t-netbsd64"
;; ;;
spu-*-elf*)
tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h"
tmake_file="spu/t-spu-elf"
extra_headers="spu_intrinsics.h spu_internals.h vmx2spu.h spu_mfcio.h vec_types.h"
extra_modes=spu/spu-modes.def
c_target_objs="${c_target_objs} spu-c.o"
cxx_target_objs="${cxx_target_objs} spu-c.o"
;;
strongarm-*-elf*) strongarm-*-elf*)
tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h" tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
tmake_file="arm/t-arm arm/t-strongarm-elf" tmake_file="arm/t-arm arm/t-strongarm-elf"
......
gcc/config/spu/constraints.md 0 → 100644
;; Constraint definitions for SPU
;; Copyright (C) 2006 Free Software Foundation, Inc.
;;
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 2 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with this file; see the file COPYING. If not, write to the Free
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
;; 02110-1301, USA.
;; GCC standard constraints: g, i, m, n, o, p, r, s, E-H, I-P, V, X
;; unused for SPU: E-H, L, Q, d, e, h, j-l, q, t-z
;; For most immediate constraints we have 3 variations to deal with the
;; fact const_int has no mode. One variation treats const_int as 32 bit,
;; another treats it as 64 bit, and the third sign extends it to 128 bit.
(define_constraint "A"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value."
(ior (and (match_code "const_int,const_double,const_vector")
(match_test "immediate_load_p (op, SImode)"))
(and (match_test "!TARGET_LARGE_MEM && !flag_pic")
(ior (match_code "symbol_ref,label_ref")
(and (match_code "const")
(match_test "legitimate_const (op, 0)"))))))
(define_constraint "B"
"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "arith_immediate_p (op, SImode, -0x200, 0x1ff)")))
(define_constraint "C"
"An immediate for and/xor/or instructions. const_int is treated as a 32 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "logical_immediate_p (op, SImode)")))
(define_constraint "D"
"An immediate for iohl instruction. const_int is treated as a 32 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "iohl_immediate_p (op, SImode)")))
(define_constraint "U"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "immediate_load_p (op, TImode)")))
(define_constraint "W"
"An immediate for shift and rotate instructions. const_int is treated as a 32 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "arith_immediate_p (op, SImode, -0x40, 0x3f)")))
(define_constraint "Y"
"An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "logical_immediate_p (op, TImode)")))
(define_constraint "Z"
"An immediate for iohl instruction. const_int is sign extended to 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "iohl_immediate_p (op, TImode)")))
(define_constraint "a"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value."
(and (match_code "const_int")
(match_test "immediate_load_p (op, DImode)")))
(define_constraint "c"
"An immediate for and/xor/or instructions. const_int is treated as a 64 bit value."
(and (match_code "const_int")
(match_test "logical_immediate_p (op, DImode)")))
(define_constraint "d"
"An immediate for iohl instruction. const_int is treated as a 64 bit value."
(and (match_code "const_int")
(match_test "iohl_immediate_p (op, DImode)")))
(define_constraint "f"
"An immediate which can be loaded with fsmbi."
(and (match_code "const_int,const_double,const_vector")
(match_test "fsmbi_const_p (op)")))
;; Integer constraints
(define_constraint "I"
"A constant in the range [-64, 63] for shift/rotate instructions."
(and (match_code "const_int")
(match_test "ival >= -0x40 && ival <= 0x3f")))
(define_constraint "J"
"An unsigned 7-bit constant for conversion/nop/channel instructions."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 0x7f")))
(define_constraint "K"
"A signed 10-bit constant for most arithmetic instructions."
(and (match_code "const_int")
(match_test "ival >= -0x200 && ival <= 0x1ff")))
(define_constraint "M"
"A signed 16 bit immediate for @code{stop}."
(and (match_code "const_int")
(match_test "ival >= -0x8000ll && ival <= 0x7fffll")))
(define_constraint "N"
"An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 0xffff")))
(define_constraint "O"
"An unsigned 7-bit constant whose 3 least significant bits are 0."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 0x7f && (ival & 7) == 0")))
(define_constraint "P"
"An unsigned 3-bit constant for 16-byte rotates and shifts"
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 7")))
;; Memory constraints
(define_memory_constraint "R"
"Call operand, reg, for indirect calls"
(and (match_code "mem")
(match_test "GET_CODE(XEXP(op, 0)) == REG")))
(define_memory_constraint "S"
"Call operand, symbol, for relative calls."
(and (match_code "mem")
(match_test "!TARGET_LARGE_MEM
&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF))")))
(define_memory_constraint "T"
"Call operand, const_int, for absolute calls."
(and (match_code "mem")
(match_test "GET_CODE (XEXP (op, 0)) == CONST_INT
&& INTVAL (XEXP (op, 0)) >= 0
&& INTVAL (XEXP (op, 0)) <= 0x3ffff")))
gcc/config/spu/crt0.c 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you link this library with files compiled with
GCC to produce an executable, this does not cause the resulting executable
to be covered by the GNU General Public License. The exception does not
however invalidate any other reasons why the executable file might be covered
by the GNU General Public License. */
extern int main(int, unsigned long long, unsigned long long);
void _start(int, unsigned long long, unsigned long long) __attribute__((__naked__));
extern void exit(int);
void _exit(int) __attribute__((__naked__));
typedef void (*func_ptr) (void);
typedef __attribute__ ((__vector_size__(16))) unsigned int vec_uint4;
extern vec_uint4 __stack[];
register vec_uint4 si_sp __asm__("$sp");
register unsigned int si_r2 __asm__("$2");
extern char _end[];
/* If we want these aligned we need to do it in the linker script. */
func_ptr __CTOR_LIST__[1]
__attribute__ ((__section__(".ctors"), __aligned__(4)))
= { (func_ptr) (-1) };
static func_ptr __DTOR_LIST__[1]
__attribute__((__section__(".dtors"), __aligned__(4)))
= { (func_ptr) (-1) };
/* According to the BE Linux ABI an SPU module is called with these
* parameters. Also, $2 is set to the Available Stack Size. */
void
_start(int spu_id,
unsigned long long param,
unsigned long long env)
{
unsigned int stack_size;
unsigned int sp = (unsigned int)(__stack - 2);
/* Initialize the stack. __stack has been set to point to the top
quadword of the stack. The ABI requires at least a NULL terminated
back chain and lr save area. For example:
+----------------+
| 0 |
+----------------+ <- __stack (e.g., 0x3fff0)
| space for $lr |
+----------------+
| back chain |
+----------------+ <- $sp (e.g., __stack - 32, 0x3ffd0)
*/
__stack[0] = (vec_uint4){0, 0, 0, 0};
__stack[-1] = (vec_uint4){0, 0, 0, 0};
/* Initialize the Available Stack Size word of the Stack Pointer
* information register. The BE Linux ABI passes the stack size in
* $2, or use everything up to _end if $2 == 0. */
stack_size = si_r2 == 0 ? sp - (unsigned int)_end : si_r2;
__stack[-2] = (vec_uint4){(unsigned int)__stack, stack_size, 0, 0};
si_sp = (vec_uint4){sp, stack_size, 0, 0};
{
extern func_ptr __CTOR_END__[];
func_ptr *p;
/* The compiler assumes all symbols are 16 byte aligned, which is
* not the case for __CTOR_END__. This inline assembly makes sure
* the address is loaded into a register for which the compiler does
* not assume anything about alignment. */
__asm__ ("\n" : "=r" (p) : "0" (__CTOR_END__ - 1));
for (; *p != (func_ptr) -1; p--)
(*p) ();
}
exit(main(spu_id, param, env));
__asm__ volatile ( " stop 0x20ff");
}
/* C99 requires _Exit */
void _Exit(int) __attribute__((__weak__, __alias__("_exit")));
void
_exit(int rc)
{
{
static func_ptr *p = 0;
if (!p)
{
/* See comment for __CTOR_END__ above. */
__asm__ ("" : "=r" (p) : "0" (__DTOR_LIST__ + 1));
for (; *p; p++)
(*p) ();
}
}
/* Some self modifying code to return 'rc' in the 'stop' insn. */
__asm__ volatile (
" ori $3, %0,0\n"
" lqr $4, 1f\n"
" cbd $5, 1f+3($sp)\n"
" shufb $0, %0, $4, $5\n"
" stqr $0, 1f\n"
" sync\n"
"1:\n"
" stop 0x2000\n"
: : "r" (rc) );
}
gcc/config/spu/crtend.c 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you link this library with files compiled with
GCC to produce an executable, this does not cause the resulting executable
to be covered by the GNU General Public License. The exception does not
however invalidate any other reasons why the executable file might be covered
by the GNU General Public License. */
typedef void (*func_ptr) (void);
func_ptr __CTOR_END__[1]
__attribute__ ((section(".ctors"), aligned(sizeof(func_ptr))))
= { (func_ptr) (0) };
func_ptr __DTOR_END__[1]
__attribute__((section(".dtors"), aligned(sizeof(func_ptr))))
= { (func_ptr) (0) };
gcc/config/spu/crti.asm 0 → 100644
# Copyright (C) 2006 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This file is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License
# along with this file; see the file COPYING. If not, write to the Free
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA. */
#
# As a special exception, if you link this library with files
# compiled with GCC to produce an executable, this does not cause
# the resulting executable to be covered by the GNU General Public License.
# This exception does not however invalidate any other reasons why
# the executable file might be covered by the GNU General Public License.
#
# This file just make a stack frame for the contents of the .fini and
# .init sections. Users may put any desired instructions in those
# sections.
# Note - this macro is complimented by the FUNC_END macro
# in crtn.asm. If you change this macro you must also change
# that macro match.
.macro FUNC_START
# Create a stack frame and save any call-preserved registers
ai $sp, $sp, -16
stqd $lr, 0($sp)
.endm
.file "crti.asm"
.section ".init"
.align 2
.global _init
_init:
FUNC_START
.section ".fini"
.align 2
.global _fini
_fini:
FUNC_START
# end of crti.asm
gcc/config/spu/crtn.asm 0 → 100644
# Copyright (C) 2006 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This file is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License
# along with this file; see the file COPYING. If not, write to the Free
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA. */
#
# As a special exception, if you link this library with files
# compiled with GCC to produce an executable, this does not cause
# the resulting executable to be covered by the GNU General Public License.
# This exception does not however invalidate any other reasons why
# the executable file might be covered by the GNU General Public License.
#
# This file just makes sure that the .fini and .init sections do in
# fact return. Users may put any desired instructions in those sections.
# This file is the last thing linked into any executable.
# Note - this macro is complimented by the FUNC_START macro
# in crti.asm. If you change this macro you must also change
# that macro match.
#
# Note - we do not try any fancy optimisations of the return
# sequences here, it is just not worth it. Instead keep things
# simple. Restore all the save resgisters, including the link
# register and then perform the correct function return instruction.
.macro FUNC_END
lqd $lr, 0($sp)
ai $sp, $sp, 16
bi $lr
.endm
.file "crtn.asm"
.section ".init"
;;
FUNC_END
.section ".fini"
;;
FUNC_END
# end of crtn.asm
gcc/config/spu/float_unsdidf.c 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you link this library with files compiled with
GCC to produce an executable, this does not cause the resulting executable
to be covered by the GNU General Public License. The exception does not
however invalidate any other reasons why the executable file might be covered
by the GNU General Public License. */
#include <spu_intrinsics.h>
const unsigned char __didf_scale[16] __attribute__ ((__aligned__ (16))) = {
0x00, 0x00, 0x04, 0x3e,
0x00, 0x00, 0x04, 0x1e,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
const unsigned char __didf_pat[16] __attribute__ ((__aligned__ (16))) = {
0x02, 0x03, 0x10, 0x11,
0x12, 0x13, 0x80, 0x80,
0x06, 0x07, 0x14, 0x15,
0x16, 0x17, 0x80, 0x80
};
/* double __float_unsdidf (unsigned long long int)
Construct two exact doubles representing the high and low parts (in
parallel), then add them. */
qword __float_unsdidf (qword DI);
qword
__float_unsdidf (qword DI)
{
qword t0, t1, t2, t3, t4, t5, t6, t7, t8;
t0 = si_clz (DI);
t1 = si_shl (DI, t0);
t2 = si_ceqi (t0, 32);
t3 = si_sf (t0, *(qword *) __didf_scale);
t4 = si_a (t1, t1);
t5 = si_andc (t3, t2);
t6 = si_shufb (t5, t4, *(qword *) __didf_pat);
t7 = si_shlqbii (t6, 4);
t8 = si_shlqbyi (t7, 8);
return si_dfa (t7, t8);
}
gcc/config/spu/float_unssidf.c 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you link this library with files compiled with
GCC to produce an executable, this does not cause the resulting executable
to be covered by the GNU General Public License. The exception does not
however invalidate any other reasons why the executable file might be covered
by the GNU General Public License. */
#include <spu_intrinsics.h>
const unsigned char __sidf_pat[16] __attribute__ ((__aligned__ (16))) = {
0x02, 0x03, 0x10, 0x11,
0x12, 0x13, 0x80, 0x80,
0x06, 0x07, 0x14, 0x15,
0x16, 0x17, 0x80, 0x80
};
/* double __float_unssidf (unsigned int SI) */
qword __float_unssidf (qword SI);
qword
__float_unssidf (qword SI)
{
qword t0, t1, t2, t3, t4, t5, t6, t7;
t0 = si_clz (SI);
t1 = si_il (1054);
t2 = si_shl (SI, t0);
t3 = si_ceqi (t0, 32);
t4 = si_sf (t0, t1);
t5 = si_a (t2, t2);
t6 = si_andc (t4, t3);
t7 = si_shufb (t6, t5, *(qword *)__sidf_pat);
return si_shlqbii (t7, 4);
}
gcc/config/spu/predicates.md 0 → 100644
;; Predicate definitions for CELL SPU
;; Copyright (C) 2006 Free Software Foundation, Inc.
;;
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 2 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with this file; see the file COPYING. If not, write to the Free
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
;; 02110-1301, USA.
(define_predicate "spu_reg_operand"
(and (match_operand 0 "register_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_nonimm_operand"
(and (match_operand 0 "nonimmediate_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_nonmem_operand"
(and (match_operand 0 "nonmemory_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_mem_operand"
(and (match_operand 0 "memory_operand")
(match_test "reload_in_progress || reload_completed || aligned_mem_p (op)")))
(define_predicate "call_operand"
(and (match_code "mem")
(match_test "(!TARGET_LARGE_MEM && satisfies_constraint_S (op))
|| (satisfies_constraint_R (op)
&& REGNO (XEXP (op, 0)) != FRAME_POINTER_REGNUM
&& REGNO (XEXP (op, 0)) != ARG_POINTER_REGNUM
&& (REGNO (XEXP (op, 0)) < FIRST_PSEUDO_REGISTER
|| REGNO (XEXP (op, 0)) > LAST_VIRTUAL_REGISTER))")))
(define_predicate "vec_imm_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "spu_legitimate_constant_p (op)")))
(define_predicate "spu_arith_operand"
(match_code "reg,subreg,const_int,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
return arith_immediate_p (op, mode, -0x200, 0x1ff);
return 0;
})
(define_predicate "spu_logical_operand"
(match_code "reg,subreg,const_int,const_double,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode);
return 0;
})
(define_predicate "spu_ior_operand"
(match_code "reg,subreg,const_int,const_double,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
return 0;
})
(define_predicate "spu_shift_operand"
(match_code "reg,subreg,const_int,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
return arith_immediate_p (op, mode, -0x40, 0x3f);
return 0;
})
;; Return 1 if OP is a comparison operation that is valid for a branch insn.
;; We only check the opcode against the mode of the register value here.
(define_predicate "branch_comparison_operator"
(and (match_code "eq,ne")
(ior (match_test "GET_MODE (XEXP (op, 0)) == HImode")
(match_test "GET_MODE (XEXP (op, 0)) == SImode"))))
gcc/config/spu/spu-builtins.h 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* built-ins */
enum spu_builtin_type_index
{
SPU_BTI_END_OF_PARAMS,
/* We create new type nodes for these. */
SPU_BTI_V16QI,
SPU_BTI_V8HI,
SPU_BTI_V4SI,
SPU_BTI_V2DI,
SPU_BTI_V4SF,
SPU_BTI_V2DF,
SPU_BTI_UV16QI,
SPU_BTI_UV8HI,
SPU_BTI_UV4SI,
SPU_BTI_UV2DI,
/* A 16-byte type. (Implemented with V16QI_type_node) */
SPU_BTI_QUADWORD,
/* These all correspond to intSI_type_node */
SPU_BTI_7,
SPU_BTI_S7,
SPU_BTI_U7,
SPU_BTI_S10,
SPU_BTI_S10_4,
SPU_BTI_U14,
SPU_BTI_16,
SPU_BTI_S16,
SPU_BTI_S16_2,
SPU_BTI_U16,
SPU_BTI_U16_2,
SPU_BTI_U18,
/* These correspond to the standard types */
SPU_BTI_INTQI,
SPU_BTI_INTHI,
SPU_BTI_INTSI,
SPU_BTI_INTDI,
SPU_BTI_UINTQI,
SPU_BTI_UINTHI,
SPU_BTI_UINTSI,
SPU_BTI_UINTDI,
SPU_BTI_FLOAT,
SPU_BTI_DOUBLE,
SPU_BTI_VOID,
SPU_BTI_PTR,
SPU_BTI_MAX
};
#define V16QI_type_node (spu_builtin_types[SPU_BTI_V16QI])
#define V8HI_type_node (spu_builtin_types[SPU_BTI_V8HI])
#define V4SI_type_node (spu_builtin_types[SPU_BTI_V4SI])
#define V2DI_type_node (spu_builtin_types[SPU_BTI_V2DI])
#define V4SF_type_node (spu_builtin_types[SPU_BTI_V4SF])
#define V2DF_type_node (spu_builtin_types[SPU_BTI_V2DF])
#define unsigned_V16QI_type_node (spu_builtin_types[SPU_BTI_UV16QI])
#define unsigned_V8HI_type_node (spu_builtin_types[SPU_BTI_UV8HI])
#define unsigned_V4SI_type_node (spu_builtin_types[SPU_BTI_UV4SI])
#define unsigned_V2DI_type_node (spu_builtin_types[SPU_BTI_UV2DI])
extern GTY(()) tree spu_builtin_types[SPU_BTI_MAX];
/* Some builtins require special handling. This enum differentiates. */
enum spu_builtin_type {
B_INSN,
B_JUMP,
B_BISLED,
B_CALL,
B_HINT,
B_OVERLOAD,
B_INTERNAL
};
typedef enum {
#define DEF_BUILTIN(fcode, icode, name, type, params) fcode,
#include "spu-builtins.def"
#undef DEF_BUILTIN
NUM_SPU_BUILTINS
} spu_function_code;
struct spu_builtin_description {
spu_function_code fcode;
enum insn_code icode;
const char *name;
enum spu_builtin_type type;
/* The first element of parm is always the return type. The rest
* are a zero terminated list of parameters. */
int parm[5];
tree fndecl;
};
extern GTY(()) struct spu_builtin_description spu_builtins[];
gcc/config/spu/spu-elf.h 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef OBJECT_FORMAT_ELF
#error elf.h included before elfos.h
#endif
#define BSS_SECTION_ASM_OP "\t.section .bss"
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crt1%O%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend1%O%s"
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#define SET_ASM_OP "\t.set\t"
#undef TARGET_ASM_NAMED_SECTION
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
#define EH_FRAME_IN_DATA_SECTION 1
#define LINK_SPEC "%{mlarge-mem: --defsym __stack=0xfffffff0 }"
#define LIB_SPEC \
"-( %{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}} -lgloss -)"
/* Turn off warnings in the assembler too. */
#undef ASM_SPEC
#define ASM_SPEC "%{w:-W}"
gcc/config/spu/spu-modes.def 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* Vector modes. */
VECTOR_MODES (INT, 2); /* V2QI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
/* A special mode for the intr regsister so we can treat it differently
for conditional moves. */
RANDOM_MODE (INTR);
/* cse_insn needs an INT_MODE larger than WORD_MODE, otherwise some
parts of it will go into an infinite loop. */
INT_MODE (OI, 32);
gcc/config/spu/spu-protos.h 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef _SPU_PROTOS_
#define _SPU_PROTOS_
#include "rtl.h"
extern enum machine_mode spu_eh_return_filter_mode (void);
extern void spu_cpu_cpp_builtins (struct cpp_reader * pfile);
extern void builtin_define_std (const char *);
extern void spu_override_options (void);
extern int valid_subreg (rtx op);
extern void spu_expand_extv (rtx * ops, int unsignedp);
extern void spu_expand_insv (rtx * ops);
extern int spu_expand_block_move (rtx * ops);
extern void spu_emit_branch_or_set (int is_set, enum rtx_code code,
rtx * operands);
extern HOST_WIDE_INT const_double_to_hwint (rtx x);
extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v);
extern void print_operand_address (FILE * file, register rtx addr);
extern void print_operand (FILE * file, rtx x, int code);
extern int spu_saved_regs_size (void);
extern int direct_return (void);
extern void spu_expand_prologue (void);
extern void spu_expand_epilogue (unsigned char sibcall_p);
extern rtx spu_return_addr (int count, rtx frame);
extern rtx spu_const (enum machine_mode mode, HOST_WIDE_INT val);
extern struct rtx_def *spu_float_const (const char *string,
enum machine_mode mode);
extern int immediate_load_p (rtx op, enum machine_mode mode);
extern int logical_immediate_p (rtx op, enum machine_mode mode);
extern int iohl_immediate_p (rtx op, enum machine_mode mode);
extern int arith_immediate_p (rtx op, enum machine_mode mode,
HOST_WIDE_INT low, HOST_WIDE_INT high);
extern int legitimate_const (rtx x, int aligned);
extern int spu_constant_address_p (rtx x);
extern int spu_legitimate_constant_p (rtx x);
extern int spu_legitimate_address (enum machine_mode mode, rtx x,
int reg_ok_strict);
extern rtx spu_legitimize_address (rtx x, rtx oldx, enum machine_mode mode);
extern int spu_initial_elimination_offset (int from, int to);
extern rtx spu_function_value (tree type, tree func);
extern rtx spu_function_arg (int cum, enum machine_mode mode, tree type,
int named);
extern void spu_va_start (tree valist, rtx nextarg);
extern void spu_setup_incoming_varargs (int *cum, enum machine_mode mode,
tree type, int *pretend_size,
int no_rtl);
extern void spu_conditional_register_usage (void);
extern int aligned_mem_p (rtx mem);
extern int spu_expand_mov (rtx * ops, enum machine_mode mode);
extern void spu_split_load (rtx * ops);
extern void spu_split_store (rtx * ops);
extern int spu_valid_move (rtx * ops);
extern int fsmbi_const_p (rtx x);
extern void constant_to_array (enum machine_mode mode, rtx x,
unsigned char *arr);
extern rtx array_to_constant (enum machine_mode mode, unsigned char *arr);
extern enum machine_mode spu_eh_return_filter_mode (void);
extern void spu_allocate_stack (rtx op0, rtx op1);
extern void spu_restore_stack_nonlocal (rtx op0, rtx op1);
extern rtx spu_gen_subreg (enum machine_mode mode, rtx x);
extern int spu_safe_dma(HOST_WIDE_INT channel);
extern void spu_builtin_splats (rtx ops[]);
extern void spu_builtin_extract (rtx ops[]);
extern void spu_builtin_insert (rtx ops[]);
extern void spu_builtin_promote (rtx ops[]);
extern void spu_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt);
extern void spu_expand_sign_extend (rtx ops[]);
extern void spu_expand_vector_init (rtx target, rtx vals);
/* spu-c.c */
extern tree spu_resolve_overloaded_builtin (tree fndecl, tree fnargs);
extern rtx spu_expand_builtin (tree exp, rtx target, rtx subtarget,
enum machine_mode mode, int ignore);
extern rtx spu_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
#endif
gcc/config/spu/spu.c 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/spu/spu.opt 0 → 100644
; Options for the SPU port of the compiler
; Copyright (C) 2006 Free Software Foundation, Inc.
; This file is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 2 of the License, or (at your option)
; any later version.
; This file is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with this file; see the file COPYING. If not, write to the Free
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
; 02110-1301, USA.
mwarn-reloc
Target Report Mask(WARN_RELOC)
Emit warnings when run-time relocations are generated
merror-reloc
Target Report Mask(ERROR_RELOC)
Emit errors when run-time relocations are generated
mbranch-cost=
Target RejectNegative Joined UInteger Var(spu_branch_cost) Init(20)
Specify cost of branches (Default 20)
msafe-dma
Target Report RejectNegative Mask(SAFE_DMA)
Make sure loads and stores are not moved past DMA instructions
munsafe-dma
Target Report RejectNegative InverseMask(SAFE_DMA)
volatile must be specified on any memory that is effected by DMA
mbranch-hints
Target Report Mask(BRANCH_HINTS)
Generate branch hints for branches
msmall-mem
Target Report RejectNegative InverseMask(LARGE_MEM)
Generate code for 18 bit addressing
mlarge-mem
Target Report RejectNegative Mask(LARGE_MEM)
Generate code for 32 bit addressing
gcc/config/spu/spu_internals.h 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/spu/spu_intrinsics.h 0 → 100644
/* Definitions of Synergistic Processing Unit (SPU). */
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you include this header file into source files
compiled by GCC, this header file does not by itself cause the resulting
executable to be covered by the GNU General Public License. This exception
does not however invalidate any other reasons why the executable file might be
covered by the GNU General Public License. */
#ifndef _SPU_INTRINSICS_H
#define _SPU_INTRINSICS_H
#define vec_uchar16 __vector unsigned char
#define vec_char16 __vector signed char
#define vec_ushort8 __vector unsigned short
#define vec_short8 __vector signed short
#define vec_uint4 __vector unsigned int
#define vec_int4 __vector signed int
#define vec_ullong2 __vector unsigned long long
#define vec_llong2 __vector signed long long
#define vec_float4 __vector float
#define vec_double2 __vector double
/* SPU Channel Defines
*/
#define SPU_RdEventStat 0
#define SPU_WrEventMask 1
#define SPU_WrEventAck 2
#define SPU_RdSigNotify1 3
#define SPU_RdSigNotify2 4
#define SPU_WrDec 7
#define SPU_RdDec 8
#define SPU_RdEventStatMask 11
#define SPU_RdMachStat 13
#define SPU_WrSRR0 14
#define SPU_RdSRR0 15
#define SPU_WrOutMbox 28
#define SPU_RdInMbox 29
#define SPU_WrOutIntrMbox 30
/* MFC Channel Defines.
*/
#define MFC_WrMSSyncReq 9
#define MFC_RdTagMask 12
#define MFC_LSA 16
#define MFC_EAH 17
#define MFC_EAL 18
#define MFC_Size 19
#define MFC_TagID 20
#define MFC_Cmd 21
#define MFC_WrTagMask 22
#define MFC_WrTagUpdate 23
#define MFC_RdTagStat 24
#define MFC_RdListStallStat 25
#define MFC_WrListStallAck 26
#define MFC_RdAtomicStat 27
#include <spu_internals.h>
#endif /* _SPU_INTRINSICS_H */
gcc/config/spu/t-spu-elf 0 → 100644
# Copyright (C) 2006 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This file is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License
# along with this file; see the file COPYING. If not, write to the Free
# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
# Suppress building libgcc1.a
LIBGCC1 =
CROSS_LIBGCC1 =
# On SPU __word__ is TImode which is too inefficient and incomplete for
# implementing libgcc routines.
TARGET_LIBGCC2_CFLAGS = -fPIC -D__word__=SI -mwarn-reloc
LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/spu/float_unssidf.c \
$(srcdir)/config/spu/float_unsdidf.c
LIB2ADDEH = $(srcdir)/unwind-dw2.c $(srcdir)/unwind-dw2-fde.c \
$(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c $(srcdir)/config/spu/t-spu-elf
echo '#undef US_SOFTWARE_GOFAST' > dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c $(srcdir)/config/spu/t-spu-elf
echo '#define FLOAT' > fp-bit.c
echo '#undef US_SOFTWARE_GOFAST' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
# Don't let CTOR_LIST end up in sdata section.
CRTSTUFF_T_CFLAGS =
#MULTILIB_OPTIONS=mlarge-mem/mtest-abi
#MULTILIB_DIRNAMES=large-mem test-abi
#MULTILIB_MATCHES=
# Neither gcc or newlib seem to have a standard way to generate multiple
# crt*.o files. So we don't use the standard crt0.o name anymore.
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o crt1.o crtend1.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Assemble startup files.
$(T)crti.o: $(srcdir)/config/spu/crti.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/spu/crti.asm
$(T)crtn.o: $(srcdir)/config/spu/crtn.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/spu/crtn.asm
$(T)crt1.o: $(srcdir)/config/spu/crt0.c $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-O2 \
-c -o $(T)crt1.o $(srcdir)/config/spu/crt0.c
$(T)crtend1.o: $(srcdir)/config/spu/crtend.c $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-O2 \
-c -o $(T)crtend1.o $(srcdir)/config/spu/crtend.c
spu.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
$(RTL_H) $(REGS_H) hard-reg-set.h \
real.h insn-config.h conditions.h insn-attr.h flags.h $(RECOG_H) \
$(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \
output.h $(BASIC_BLOCK_H) $(INTEGRATE_H) toplev.h $(GGC_H) $(HASHTAB_H) \
$(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h cfglayout.h \
$(srcdir)/config/spu/spu-protos.h \
$(srcdir)/config/spu/spu-builtins.h \
$(srcdir)/config/spu/spu-builtins.def
spu-c.o: $(srcdir)/config/spu/spu-c.c \
$(srcdir)/config/spu/spu-protos.h \
$(srcdir)/config/spu/spu-builtins.h \
$(srcdir)/config/spu/spu-builtins.def \
$(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(CPPLIB_H) \
$(TM_P_H) c-pragma.h errors.h coretypes.h $(TM_H) insn-codes.h
$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/spu/spu-c.c
gcc/config/spu/vec_types.h 0 → 100644
/* Copyright (C) 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA. */
/* As a special exception, if you include this header file into source files
compiled by GCC, this header file does not by itself cause the resulting
executable to be covered by the GNU General Public License. This exception
does not however invalidate any other reasons why the executable file might be
covered by the GNU General Public License. */
#ifndef _VEC_TYPES_H_
#define _VEC_TYPES_H_ 1
#include <spu_intrinsics.h>
/* Define additional PowerPC SIMD/Vector Multi-media eXtension
* single keyword vector data types for use in mapping VMX code
* to the SPU.
*/
#define vec_bchar16 __vector unsigned char
#define vec_bshort8 __vector unsigned short
#define vec_pixel8 __vector unsigned short
#define vec_bint4 __vector unsigned int
#endif /* _VEC_TYPES_H_ */
gcc/doc/contrib.texi
...@@ -822,6 +822,9 @@ for GNU/Linux. ...@@ -822,6 +822,9 @@ for GNU/Linux.
Andrey Slepuhin for assorted AIX hacking. Andrey Slepuhin for assorted AIX hacking.
@item @item
Trevor Smigiel for contributing the SPU port.
@item
Christopher Smith did the port for Convex machines. Christopher Smith did the port for Convex machines.
@item @item
......
gcc/doc/extend.texi
...@@ -2054,8 +2054,8 @@ defined by shared libraries. ...@@ -2054,8 +2054,8 @@ defined by shared libraries.
@item naked @item naked
@cindex function without a prologue/epilogue code @cindex function without a prologue/epilogue code
Use this attribute on the ARM, AVR, C4x and IP2K ports to indicate that the Use this attribute on the ARM, AVR, C4x, IP2K and SPU ports to indicate that
specified function does not need prologue/epilogue sequences generated by the specified function does not need prologue/epilogue sequences generated by
the compiler. It is up to the programmer to provide these sequences. the compiler. It is up to the programmer to provide these sequences.
@item near @item near
...@@ -3416,6 +3416,12 @@ documentation in the @xref{i386 Variable Attributes}, section. ...@@ -3416,6 +3416,12 @@ documentation in the @xref{i386 Variable Attributes}, section.
For documentation of @code{altivec} attribute please see the For documentation of @code{altivec} attribute please see the
documentation in the @xref{PowerPC Type Attributes}, section. documentation in the @xref{PowerPC Type Attributes}, section.
@subsection SPU Variable Attributes
The SPU supports the @code{spu_vector} attribute for variables. For
documentation of this attribute please see the documentation in the
@xref{SPU Type Attributes}, section.
@subsection Xstormy16 Variable Attributes @subsection Xstormy16 Variable Attributes
One attribute is currently defined for xstormy16 configurations: One attribute is currently defined for xstormy16 configurations:
...@@ -3795,6 +3801,15 @@ __attribute__((altivec(bool__))) unsigned ...@@ -3795,6 +3801,15 @@ __attribute__((altivec(bool__))) unsigned
These attributes mainly are intended to support the @code{__vector}, These attributes mainly are intended to support the @code{__vector},
@code{__pixel}, and @code{__bool} AltiVec keywords. @code{__pixel}, and @code{__bool} AltiVec keywords.
@anchor{SPU Type Attributes}
@subsection SPU Type Attributes
The SPU supports the @code{spu_vector} attribute for types. This attribute
allows one to declare vector data types supported by the Sony/Toshiba/IBM SPU
Language Extensions Specification. It is intended to support the
@code{__vector} keyword.
@node Inline @node Inline
@section An Inline Function is As Fast As a Macro @section An Inline Function is As Fast As a Macro
@cindex inline functions @cindex inline functions
...@@ -6157,6 +6172,7 @@ instructions, but allow the compiler to schedule those calls. ...@@ -6157,6 +6172,7 @@ instructions, but allow the compiler to schedule those calls.
* MIPS Paired-Single Support:: * MIPS Paired-Single Support::
* PowerPC AltiVec Built-in Functions:: * PowerPC AltiVec Built-in Functions::
* SPARC VIS Built-in Functions:: * SPARC VIS Built-in Functions::
* SPU Built-in Functions::
@end menu @end menu
@node Alpha Built-in Functions @node Alpha Built-in Functions
...@@ -9736,6 +9752,62 @@ v8qi __builtin_vis_fpmerge (v4qi, v4qi); ...@@ -9736,6 +9752,62 @@ v8qi __builtin_vis_fpmerge (v4qi, v4qi);
int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t); int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
@end smallexample @end smallexample
@node SPU Built-in Functions
@subsection SPU Built-in Functions
GCC provides extensions for the SPU processor as described in the
Sony/Toshiba/IBM SPU Language Extensions Specification, which can be
found at @uref{http://cell.scei.co.jp/} or
@uref{http://www.ibm.com/developerworks/power/cell/}. GCC's
implementation differs in several ways.
@itemize @bullet
@item
The optional extension of specifying vector constants in parentheses is
not supported.
@item
A vector initializer requires no cast if the vector constant is of the
same type as the variable it is initializing.
@item
If @code{signed} or @code{unsigned} is omitted, the signedness of the
vector type is the default signedness of the base type. The default
varies depending on the operating system, so a portable program should
always specify the signedness.
@item
By default, the keyword @code{__vector} is added. The macro
@code{vector} is defined in @code{<spu_intrinsics.h>} and can be
undefined.
@item
GCC allows using a @code{typedef} name as the type specifier for a
vector type.
@item
For C, overloaded functions are implemented with macros so the following
does not work:
@smallexample
spu_add ((vector signed int)@{1, 2, 3, 4@}, foo);
@end smallexample
Since @code{spu_add} is a macro, the vector constant in the example
is treated as four separate arguments. Wrap the entire argument in
parentheses for this to work.
@item
The extended version of @code{__builtin_expect} is not supported.
@end itemize
@emph{Note:} Only the interface descibed in the aforementioned
specification is supported. Internally, GCC uses built-in functions to
implement the required functionality, but these are not supported and
are subject to change without notice.
@node Target Format Checks @node Target Format Checks
@section Format Checks Specific to Particular Target Machines @section Format Checks Specific to Particular Target Machines
......
gcc/doc/invoke.texi
...@@ -728,6 +728,12 @@ See RS/6000 and PowerPC Options. ...@@ -728,6 +728,12 @@ See RS/6000 and PowerPC Options.
-mv8plus -mno-v8plus -mvis -mno-vis -mv8plus -mno-v8plus -mvis -mno-vis
-threads -pthreads -pthread} -threads -pthreads -pthread}
@emph{SPU Options}
@gccoptlist{-mwarn-reloc -merror-reloc @gol
-msafe-dma -munsafe-dma @gol
-mbranch-hints @gol
-msmall-mem -mlarge-mem}
@emph{System V Options} @emph{System V Options}
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}} @gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
...@@ -7358,6 +7364,7 @@ platform. ...@@ -7358,6 +7364,7 @@ platform.
* Score Options:: * Score Options::
* SH Options:: * SH Options::
* SPARC Options:: * SPARC Options::
* SPU Options::
* System V Options:: * System V Options::
* TMS320C3x/C4x Options:: * TMS320C3x/C4x Options::
* V850 Options:: * V850 Options::
...@@ -12781,6 +12788,57 @@ that of libraries supplied with it. ...@@ -12781,6 +12788,57 @@ that of libraries supplied with it.
This is a synonym for @option{-pthreads}. This is a synonym for @option{-pthreads}.
@end table @end table
@node SPU Options
@subsection SPU Options
@cindex SPU options
These @samp{-m} options are supported on the SPU:
@table @gcctabopt
@item -mwarn-reloc
@itemx -merror-reloc
@opindex mwarn-reloc
@opindex merror-reloc
The loader for SPU does not handle dynamic relocations. By default, GCC
will give an error when it generates code that requires a dynamic
relocation. @option{-mno-error-reloc} disables the error,
@option{-mwarn-reloc} will generate a warning instead.
@item -msafe-dma
@itemx -munsafe-dma
@opindex msafe-dma
@opindex munsafe-dma
Instructions which initiate or test completion of DMA must not be
reordered with respect to loads and stores of the memory which is being
accessed. Users typically address this problem using the volatile
keyword, but that can lead to inefficient code in places where the
memory is known to not change. Rather than mark the memory as volatile
we treat the DMA instructions as potentially effecting all memory. With
@option{-munsafe-dma} users must use the volatile keyword to protect
memory accesses.
@item -mbranch-hints
@opindex mbranch-hints
By default, GCC will generate a branch hint instruction to avoid
pipeline stalls for always taken or probably taken branches. A hint
will not be generated closer than 8 instructions away from its branch.
There is little reason to disable them, except for debugging purposes,
or to make an object a little bit smaller.
@item -msmall-mem
@itemx -mlarge-mem
@opindex msmall-mem
@opindex mlarge-mem
By default, GCC generates code assuming that addresses are never larger
than 18 bits. With @option{-mlarge-mem} code is generated that assumes
a full 32 bit address.
@end table
@node System V Options @node System V Options
@subsection Options for System V @subsection Options for System V
......
gcc/doc/md.texi
...@@ -2630,6 +2630,76 @@ Vector zero ...@@ -2630,6 +2630,76 @@ Vector zero
@end table @end table
@item SPU---@file{config/spu/spu.h}
@table @code
@item a
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
@item c
An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
@item d
An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
@item f
An immediate which can be loaded with @code{fsmbi}.
@item A
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
@item B
An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
@item C
An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
@item D
An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
@item I
A constant in the range [-64, 63] for shift/rotate instructions.
@item J
An unsigned 7-bit constant for conversion/nop/channel instructions.
@item K
A signed 10-bit constant for most arithmetic instructions.
@item M
A signed 16 bit immediate for @code{stop}.
@item N
An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
@item O
An unsigned 7-bit constant whose 3 least significant bits are 0.
@item P
An unsigned 3-bit constant for 16-byte rotates and shifts
@item R
Call operand, reg, for indirect calls
@item S
Call operand, symbol, for relative calls.
@item T
Call operand, const_int, for absolute calls.
@item U
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
@item W
An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
@item Y
An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
@item Z
An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
@end table
@item TMS320C3x/C4x---@file{config/c4x/c4x.h} @item TMS320C3x/C4x---@file{config/c4x/c4x.h}
@table @code @table @code
@item a @item a
......
libcpp/ChangeLog
2006-11-20 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
* configure.ac (need_64bit_hwint): Need 64bit hwint for SPU.
* configure : Rebuilt.
2006-11-01 Douglas Gregor <doug.gregor@gmail.com> 2006-11-01 Douglas Gregor <doug.gregor@gmail.com>
* include/cpplib.h (enum c_lang): Add CLK_GNUCXX0X and CLK_CXX0X * include/cpplib.h (enum c_lang): Add CLK_GNUCXX0X and CLK_CXX0X
......
libcpp/configure
...@@ -8244,6 +8244,7 @@ case $target in ...@@ -8244,6 +8244,7 @@ case $target in
sparc64*-*-* | ultrasparc-*-freebsd* | \ sparc64*-*-* | ultrasparc-*-freebsd* | \
sparcv9-*-solaris2* | \ sparcv9-*-solaris2* | \
sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \ sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
spu-*-* | \
sh[123456789l]*-*-*) sh[123456789l]*-*-*)
need_64bit_hwint=yes ;; need_64bit_hwint=yes ;;
i[34567]86-*-linux*) i[34567]86-*-linux*)
......
libcpp/configure.ac
...@@ -128,6 +128,7 @@ case $target in ...@@ -128,6 +128,7 @@ case $target in
sparc64*-*-* | ultrasparc-*-freebsd* | \ sparc64*-*-* | ultrasparc-*-freebsd* | \
sparcv9-*-solaris2* | \ sparcv9-*-solaris2* | \
sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \ sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
spu-*-* | \
sh[123456789l]*-*-*) sh[123456789l]*-*-*)
need_64bit_hwint=yes ;; need_64bit_hwint=yes ;;
i[34567]86-*-linux*) i[34567]86-*-linux*)
......
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