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Commit 859abddd by Sofiane Naci Committed by Sofiane Naci
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arm.md (attribute "insn"): Delete. 

	* config/arm/arm.md (attribute "insn"): Delete.
	(attribute "type"): Add "mov_imm", "mov_reg", "mov_shift",
	"mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg".
	(not_shiftsi): Update for attribute change.
	(not_shiftsi_compare0): Likewise.
	(not_shiftsi_compare0_scratch): Likewise.
	(arm_one_cmplsi2): Likewise.
	(thumb1_one_cmplsi2): Likewise.
	(notsi_compare0): Likewise.
	(notsi_compare0_scratch): Likewise.
	(thumb1_movdi_insn): Likewise.
	(arm_movsi_insn): Likewise.
	(movhi_insn_arch4): Likewise.
	(movhi_bytes): Likewise.
	(arm_movqi_insn): Likewise.
	(thumb1_movqi_insn): Likewise.
	(arm32_movhf): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_insn): Likewise.
	(thumb_movdf_insn): Likewise.
	(movsicc_insn): Likewise.
	(movsfcc_soft_insn): Likewise.
	(and_scc): Likewise.
	(cond_move): Likewise.
	(if_move_not): Likewise.
	(if_not_move): Likewise.
	(if_shift_move): Likewise.
	(if_move_shift): Likewise.
	(if_shift_shift): Likewise.
	(if_not_arith): Likewise.
	(if_arith_not): Likewise.
	(cond_move_not): Likewise.
	* config/arm/neon.md (neon_mov<mode>): Update for attribute change.
	(neon_mov<mode>): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute change.
	(thumb2_movsi_vfp): Likewise.
	(movsf_vfp): Likewise.
	(thumb2_movsf_vfp): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change.
	(cortexa7_older_only): Likewise.
	(cortexa7_younger): Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute change.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute change.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute change.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute change.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	(cortex_a8_mov): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change.
	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md (526_alu_op): Update for attribute change.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Update for attribute change.
	* config/arm/fa626te.md (626te_alu_op): Update for attribute change.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_shift_op): Update for attribute change.
	(726te_alu_op): Likewise.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute change.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change.
	(pj4_alu_e1_conds): Likewise.
	(pj4_alu): Likewise.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.

From-SVN: r201124
parent 119b97c3
Showing with 208 additions and 92 deletions
gcc/ChangeLog
2013-07-22 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/arm.md (attribute "insn"): Delete.
(attribute "type"): Add "mov_imm", "mov_reg", "mov_shift",
"mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg".
(not_shiftsi): Update for attribute change.
(not_shiftsi_compare0): Likewise.
(not_shiftsi_compare0_scratch): Likewise.
(arm_one_cmplsi2): Likewise.
(thumb1_one_cmplsi2): Likewise.
(notsi_compare0): Likewise.
(notsi_compare0_scratch): Likewise.
(thumb1_movdi_insn): Likewise.
(arm_movsi_insn): Likewise.
(movhi_insn_arch4): Likewise.
(movhi_bytes): Likewise.
(arm_movqi_insn): Likewise.
(thumb1_movqi_insn): Likewise.
(arm32_movhf): Likewise.
(thumb1_movhf): Likewise.
(arm_movsf_soft_insn): Likewise.
(thumb1_movsf_insn): Likewise.
(thumb_movdf_insn): Likewise.
(movsicc_insn): Likewise.
(movsfcc_soft_insn): Likewise.
(and_scc): Likewise.
(cond_move): Likewise.
(if_move_not): Likewise.
(if_not_move): Likewise.
(if_shift_move): Likewise.
(if_move_shift): Likewise.
(if_shift_shift): Likewise.
(if_not_arith): Likewise.
(if_arith_not): Likewise.
(cond_move_not): Likewise.
* config/arm/neon.md (neon_mov<mode>): Update for attribute change.
(neon_mov<mode>): Likewise.
* config/arm/vfp.md (arm_movsi_vfp): Update for attribute change.
(thumb2_movsi_vfp): Likewise.
(movsf_vfp): Likewise.
(thumb2_movsf_vfp): Likewise.
* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change.
(cortexa7_older_only): Likewise.
(cortexa7_younger): Likewise.
* config/arm/arm1020e.md (1020alu_op): Update for attribute change.
(1020alu_shift_op): Likewise.
(1020alu_shift_reg_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Update for attribute change.
(alu_shift_op): Likewise.
(alu_shift_reg_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Update for attribute change.
(11_alu_shift_op): Likewise.
(11_alu_shift_reg_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Update for attribute change.
(9_alu_shift_reg_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change.
(cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change.
(cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change.
(cortex_a8_alu_shift): Likewise.
(cortex_a8_alu_shift_reg): Likewise.
(cortex_a8_mov): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
(cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change.
* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change.
(cortex_r4_mov): Likewise.
(cortex_r4_alu_shift): Likewise.
(cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md (526_alu_op): Update for attribute change.
(526_alu_shift_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Update for attribute change.
* config/arm/fa626te.md (626te_alu_op): Update for attribute change.
(626te_alu_shift_op): Likewise.
* config/arm/fa726te.md (726te_shift_op): Update for attribute change.
(726te_alu_op): Likewise.
(726te_alu_shift_op): Likewise.
(726te_alu_shift_reg_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Update for attribute change.
(mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change.
(pj4_alu_e1_conds): Likewise.
(pj4_alu): Likewise.
(pj4_alu_conds): Likewise.
(pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
2013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/predicates.md (shiftable_operator_strict_it):
......
gcc/config/arm/arm.c
......@@ -8653,7 +8653,12 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
&& (attr_type == TYPE_ARLO_SHIFT || attr_type == TYPE_ARLO_SHIFT_REG))
&& (attr_type == TYPE_ARLO_SHIFT
|| attr_type == TYPE_ARLO_SHIFT_REG
|| attr_type == TYPE_MOV_SHIFT
|| attr_type == TYPE_MVN_SHIFT
|| attr_type == TYPE_MOV_SHIFT_REG
|| attr_type == TYPE_MVN_SHIFT_REG))
{
rtx shifted_operand;
int opno;
......@@ -8934,12 +8939,10 @@ cortexa7_older_only (rtx insn)
if (recog_memoized (insn) < 0)
return false;
if (get_attr_insn (insn) == INSN_MOV)
return false;
switch (get_attr_type (insn))
{
case TYPE_ARLO_REG:
case TYPE_MVN_REG:
case TYPE_SHIFT:
case TYPE_SHIFT_REG:
case TYPE_LOAD_BYTE:
......@@ -8982,13 +8985,15 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
return false;
}
if (get_attr_insn (insn) == INSN_MOV)
return true;
switch (get_attr_type (insn))
{
case TYPE_ARLO_IMM:
case TYPE_EXTEND:
case TYPE_MVN_IMM:
case TYPE_MOV_IMM:
case TYPE_MOV_REG:
case TYPE_MOV_SHIFT:
case TYPE_MOV_SHIFT_REG:
case TYPE_BRANCH:
case TYPE_CALL:
return true;
......
gcc/config/arm/arm1020e.md
......@@ -66,13 +66,14 @@
;; ALU operations with no shifted operand
(define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-register operand
......@@ -81,7 +82,7 @@
;; the execute stage.
(define_insn_reservation "1020alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"1020a_e*2,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/arm1026ejs.md
......@@ -66,13 +66,14 @@
;; ALU operations with no shifted operand
(define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-register operand
......@@ -81,7 +82,7 @@
;; the execute stage.
(define_insn_reservation "alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"a_e*2,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/arm1136jfs.md
......@@ -75,13 +75,14 @@
;; ALU operations with no shifted operand
(define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-register operand
......@@ -90,7 +91,7 @@
;; the shift stage.
(define_insn_reservation "11_alu_shift_reg_op" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"e_1*2,e_2,e_3,e_wb")
;; alu_ops can start sooner, if there is no shifter dependency
......
gcc/config/arm/arm926ejs.md
......@@ -58,7 +58,9 @@
;; ALU operations with no shifted operand
(define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\
mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift"))
"e,m,w")
;; ALU operations with a shift-by-register operand
......@@ -67,7 +69,7 @@
;; the execute stage.
(define_insn_reservation "9_alu_shift_reg_op" 2
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/cortex-a15.md
......@@ -61,14 +61,16 @@
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "extend,arlo_shift")
(and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
......@@ -76,7 +78,7 @@
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "arlo_shift_reg")
(and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")
(eq_attr "neon_type" "none")))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
......
gcc/config/arm/cortex-a5.md
......@@ -58,12 +58,15 @@
(define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a5_ex1")
;; Forwarding path for unshifted operands.
......
gcc/config/arm/cortex-a53.md
......@@ -67,12 +67,15 @@
(define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "arlo_shift,arlo_shift_reg"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a53_slot_any")
;; Forwarding path for unshifted operands.
......
gcc/config/arm/cortex-a7.md
......@@ -88,9 +88,9 @@
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
(and (ior (eq_attr "type" "arlo_imm")
(and (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm")
(ior (eq_attr "type" "extend")
(and (eq_attr "insn" "mov")
(and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
(not (eq_attr "length" "8")))))
(eq_attr "neon_type" "none")))
"cortex_a7_ex2|cortex_a7_ex1")
......@@ -99,13 +99,15 @@
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
(and (eq_attr "type" "arlo_reg,shift,shift_reg")
(and (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
(and (eq_attr "type" "arlo_shift,arlo_shift_reg")
(and (eq_attr "type" "arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")
......
gcc/config/arm/cortex-a8.md
......@@ -85,30 +85,27 @@
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
(ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(not (eq_attr "insn" "mov,mvn")))
(ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(eq_attr "type" "clz")))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
(eq_attr "type" "extend,arlo_shift"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
(eq_attr "type" "arlo_shift_reg"))
"cortex_a8_default")
;; Move instructions.
(define_insn_reservation "cortex_a8_mov" 1
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg")
(eq_attr "insn" "mov,mvn")))
(eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
"cortex_a8_default")
;; Exceptions to the default latencies for data processing instructions.
......
gcc/config/arm/cortex-a9.md
......@@ -80,18 +80,17 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
(ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(and (and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(eq_attr "insn" "mov"))
(eq_attr "neon_type" "none"))))
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift")
(eq_attr "neon_type" "none")))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
(and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(not (eq_attr "insn" "mov"))))
(eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\
mvn_shift,mvn_shift_reg"))
"cortex_a9_p0_shift | cortex_a9_p1_shift")
;; Loads have a latency of 4 cycles.
......
gcc/config/arm/cortex-m4.md
......@@ -32,7 +32,9 @@
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
(ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
arlo_shift,arlo_shift_reg")
arlo_shift,arlo_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"cortex_m4_ex")
......
gcc/config/arm/cortex-r4.md
......@@ -78,24 +78,22 @@
;; for the purposes of the dual-issue constraints above.
(define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov"))))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_mov" 2
(and (eq_attr "tune_cortexr4" "yes")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "insn" "mov")))
(eq_attr "type" "mov_imm,mov_reg"))
"cortex_r4_mov")
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "extend,arlo_shift"))
(eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_alu_shift_reg" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "arlo_shift_reg"))
(eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.
......
gcc/config/arm/fa526.md
......@@ -62,12 +62,15 @@
;; ALU operations
(define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa526_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa606te.md
......@@ -62,7 +62,10 @@
;; ALU operations
(define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,
extend,arlo_shift,arlo_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
"fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa626te.md
......@@ -68,12 +68,15 @@
;; ALU operations
(define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa626te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa726te.md
......@@ -78,15 +78,15 @@
;; Move instructions.
(define_insn_reservation "726te_shift_op" 1
(and (eq_attr "tune" "fa726te")
(eq_attr "insn" "mov,mvn"))
(eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with no shifted operand will finished in 1 cycle
;; Other ALU instructions 2 cycles.
(define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand.
......@@ -95,14 +95,12 @@
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
(eq_attr "type" "extend,arlo_shift"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "726te_alu_shift_reg_op" 3
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
(eq_attr "type" "arlo_shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Multiplication Instructions
......
gcc/config/arm/fmp626.md
......@@ -63,12 +63,15 @@
;; ALU operations
(define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fmp626_core")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fmp626_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/marvell-pj4.md
......@@ -41,54 +41,54 @@
(define_insn_reservation "pj4_alu_e1" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "insn" "mov,mvn"))
(eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg")
(not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_e1_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(eq_attr "insn" "mov,mvn"))
(eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg")
(eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(not (eq_attr "insn" "mov,mvn")))
(not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(not (eq_attr "insn" "mov,mvn")))
(eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_bypass 2 "pj4_alu_shift,pj4_shift"
......
gcc/config/arm/neon.md
......@@ -61,8 +61,7 @@
}
}
[(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,f_stored,*,f_loadd,*,*,arlo_reg,load2,store2")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "type" "*,f_stored,*,f_loadd,*,*,mov_reg,load2,store2")
(set_attr "length" "4,4,4,4,4,4,8,8,8")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
......@@ -107,8 +106,7 @@
}
[(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,*,*,*,*,*,arlo_reg,load4,store4")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "type" "*,*,*,*,*,*,mov_reg,load4,store4")
(set_attr "length" "4,8,4,8,8,8,16,8,16")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
......
gcc/config/arm/vfp.md
......@@ -53,9 +53,8 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,arlo_imm,arlo_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)
......@@ -102,10 +101,9 @@
"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "type" "*,*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
(set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "insn" "mov,mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
)
......@@ -357,9 +355,8 @@
"
[(set_attr "predicable" "yes")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
(set_attr "insn" "*,*,*,*,*,*,*,*,mov")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
)
......@@ -396,9 +393,8 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
(set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
(set_attr "insn" "*,*,*,*,*,*,*,*,mov")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
......
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