re PR libstdc++/6641 (-D__USE_MALLOC doesn't link)

PR target/6641
* Split Snd constraint into Sid and Ssd.  Disparage Sid/z alternative
  of *mov<mode> insn to avoid spill failure.

From-SVN: r224177

gcc/ChangeLog

+2015-06-05  Kaz Kojima  <kkojima@gcc.gnu.org>
+
+	PR target/66410
+	* config/sh/constraints.md (Sid, Ssd): New memory constraints.
+	* config/sh/sh.md (*mov<mode>): Use Sid and Ssd alternatives
+	instead of Snd.  Disparage Sid/z alternative with '^'.
+
 2015-06-05  Aldy Hernandez  <aldyh@redhat.com>
 
 	* dwarf2out.c: Remove deferred_locations*.

gcc/config/sh/constraints.md

@@ -309,6 +309,19 @@
   (and (match_code "mem")
        (match_test "! satisfies_constraint_Sdd (op)")))
 
+(define_memory_constraint "Sid"
+  "A memory reference that uses index addressing."
+  (and (match_code "mem")
+       (match_code "plus" "0")
+       (match_code "reg" "00")
+       (match_code "reg" "01")))
+
+(define_memory_constraint "Ssd"
+  "A memory reference that excludes index and displacement addressing."
+  (and (match_code "mem")
+       (match_test "! satisfies_constraint_Sid (op)")
+       (match_test "! satisfies_constraint_Sdd (op)")))
+
 (define_memory_constraint "Sbv"
   "A memory reference, as used in SH2A bclr.b, bset.b, etc."
   (and (match_test "MEM_P (op) && GET_MODE (op) == QImode")

gcc/config/sh/sh.md

@@ -7430,18 +7430,18 @@ label:
 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
 ;; placed into delay slots.  Since there is no QImode PC relative load, the
 ;; Q constraint and general_movsrc_operand will reject it for QImode.
-;; The Snd alternatives should come before Sdd in order to avoid a preference
-;; of using r0 als the register operand for addressing modes other than
-;; displacement addressing.
+;; The Sid/Ssd alternatives should come before Sdd in order to avoid
+;; a preference of using r0 als the register operand for addressing modes
+;; other than displacement addressing.
 ;; The Sdd alternatives allow only r0 as register operand, even though on
 ;; SH2A any register could be allowed by switching to a 32 bit insn.
 ;; Generally sticking to the r0 is preferrable, since it generates smaller
 ;; code.  Obvious r0 reloads can then be eliminated with a peephole on SH2A.
 (define_insn "*mov<mode>"
   [(set (match_operand:QIHI 0 "general_movdst_operand"
-			      "=r,r,r,Snd,r,  Sdd,z,  r,l")
+			      "=r,r,r,Sid,^zr,Ssd,r,  Sdd,z,  r,l")
 	(match_operand:QIHI 1 "general_movsrc_operand"
-			       "Q,r,i,r,  Snd,z,  Sdd,l,r"))]
+			       "Q,r,i,^zr,Sid,r,  Ssd,z,  Sdd,l,r"))]
   "TARGET_SH1
    && (arith_reg_operand (operands[0], <MODE>mode)
        || arith_reg_operand (operands[1], <MODE>mode))"
@@ -7453,9 +7453,11 @@ label:
 	mov.<bw>	%1,%0
 	mov.<bw>	%1,%0
 	mov.<bw>	%1,%0
+	mov.<bw>	%1,%0
+	mov.<bw>	%1,%0
 	sts	%1,%0
 	lds	%1,%0"
-  [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
+  [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
    (set (attr "length")
 	(cond [(and (match_operand 0 "displacement_mem_operand")
 		    (not (match_operand 0 "short_displacement_mem_operand")))