re PR target/23485 ([ia64]: Integer dvide by zero doesn't raise a signal)

        PR target/23485
        * config/ia64/ia64.md (divsi3): Check divide by zero.
        (udivsi3): Likewise.
        (divdi3): Likewise.
        (udivdi3): Likewise.

From-SVN: r103331

gcc/ChangeLog

+2005-08-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/23485
+	* config/ia64/ia64.md (divsi3): Check divide by zero.
+	(udivsi3): Likewise.
+	(divdi3): Likewise.
+	(udivdi3): Likewise.
+
 2005-08-21  Jakub Jelinek  <jakub@redhat.com>
 
 	* simplify-rtx.c (simplify_immed_subreg) <case CONST_DOUBLE>: Only clear
@@ -6,14 +14,14 @@
 2005-08-21  Sebastian Pop  <pop@cri.ensmp.fr>
 
 	PR tree-optimization/23433
-        * tree-chrec.c (chrec_apply): Translate INTEGER_CST to a
-        REAL_CST when the type is SCALAR_FLOAT_TYPE_P.
+	* tree-chrec.c (chrec_apply): Translate INTEGER_CST to a
+	REAL_CST when the type is SCALAR_FLOAT_TYPE_P.
 
 2005-08-21  Sebastian Pop  <pop@cri.ensmp.fr>
 
 	PR tree-optimization/23434
-        * tree-ssa-loop-niter.c (proved_non_wrapping_p): Give up when
-        the iteration bound is not an INTEGER_CST.
+	* tree-ssa-loop-niter.c (proved_non_wrapping_p): Give up when
+	the iteration bound is not an INTEGER_CST.
 
 2005-08-21  Dorit Nuzman  <dorit@il.ibm.com>
 
@@ -419,7 +427,7 @@
 	* c-typeck.c (c_finish_loop): Likewise.
 
 2005-08-16  J"orn Rennecke <joern.rennecke@st.com>
-            Richard Shann <rshann@superh.com>
+	    Richard Shann <rshann@superh.com>
 
 	PR middle-end/20396:
 	* optabs.c (expand_binop): Take TRULY_NOOP_TRUNCATION into account.

gcc/config/ia64/ia64.md

@@ -1896,6 +1896,9 @@
   twon34 = gen_reg_rtx (XFmode);
   emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
 
+  emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
+			    CONST1_RTX (SImode)));
+  
   emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
 
   emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
@@ -1953,6 +1956,9 @@
   twon34 = gen_reg_rtx (XFmode);
   emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
 
+  emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
+			    CONST1_RTX (SImode)));
+  
   emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
 
   emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
@@ -2311,6 +2317,9 @@
   op2_xf = gen_reg_rtx (XFmode);
   expand_float (op2_xf, operands[2], 0);
 
+  emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
+			    CONST1_RTX (DImode)));
+
   if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
     emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
   else
@@ -2357,6 +2366,9 @@
   op2_xf = gen_reg_rtx (XFmode);
   expand_float (op2_xf, operands[2], 1);
 
+  emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
+			    CONST1_RTX (DImode)));
+
   if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
     emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
   else