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riscv-gcc-1
Commit 84ef5060 by Tom Wood
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(type attribute, movdi movdf insns): Add loadd. 

	(unit attribute): Delete.
	(function units): Correct simultaneity values.  Break out
	independent units.  Add conflict matrix for the 88100 load double.

From-SVN: r1948
parent af93f7bf
Showing with 64 additions and 70 deletions
gcc/config/m88k/m88k.md
......@@ -28,7 +28,7 @@
(define_expand "m88k_sccs_id"
[(match_operand:SI 0 "" "")]
""
"{ static char sccs_id[] = \"@(#)m88k.md 2.2.6.10 28 Jul 1992 10:22:08\";
"{ static char sccs_id[] = \"@(#)m88k.md 2.2.7.5 08/24/92 10:41:24\";
FAIL; }")
;; Attribute specifications
......@@ -41,7 +41,7 @@
; I'd like to write the list as this, but genattrtab won't accept it.
;
; "branch,jump,call, ; flow-control instructions
; load,store,loada, ; data unit instructions
; load,store,loadd,loada, ; data unit instructions
; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions
; spmul,dpmul,imul, ; FPU multiply instructions
; arith,bit,mov ; integer unit instructions
......@@ -49,18 +49,9 @@
; Classification of each insn. Some insns of TYPE_BRANCH are multi-word.
(define_attr "type"
"branch,jump,call,load,store,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird"
"branch,jump,call,load,store,loadd,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird"
(const_string "arith"))
; Convenience attributes.
(define_attr "unit" "bit,memory,multiply,divide,fpadd,other"
(cond [(eq_attr "type" "bit") (const_string "bit")
(eq_attr "type" "load,store") (const_string "memory")
(eq_attr "type" "spmul,dpmul,imul") (const_string "multiply")
(eq_attr "type" "spdiv,dpdiv,idiv") (const_string "divide")
(eq_attr "type" "spadd,dpadd,spcmp,dpcmp") (const_string "fpadd")]
(const_string "other")))
(define_attr "fpu" "yes,no"
(if_then_else
(eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv")
......@@ -89,7 +80,7 @@
[(and
(and
(eq_attr "type" "!branch,jump,call,marith,weird") ; required.
(eq_attr "type" "!load")) ; issue as-soon-as-possible.
(eq_attr "type" "!load,loadd")) ; issue as-soon-as-possible.
(eq_attr "fpu" "no")) ; issue as-soon-as-possible.
(eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1)
......@@ -139,76 +130,79 @@
; Consideration of writeback contention is critical to superb scheduling.
;
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; TEST READY-DELAY BUSY-DELAY [CONFLICT-LIST])
;(define_function_unit "decode" 1 1 (const_int 1) 0 1)
; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
; Describing the alu is currently not useful.
; Describing the '100 alu is currently not useful.
;(define_function_unit "alu" 1 0 (eq_attr "type"
; "!store,marith,weird") 1 0)
;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0)
(define_function_unit "alu" 1 0
(and (eq_attr "type" "loada,arith,bit,mov") (eq_attr "cpu" "!m88100")) 2 0)
(and (eq_attr "type" "loada,arith,mov") (eq_attr "cpu" "!m88100")) 2 0)
(define_function_unit "alu" 1 0
(and (eq_attr "type" "marith,weird") (eq_attr "cpu" "!m88100")) 4 0)
(define_function_unit "memory" 1 3
(and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 2)
(define_function_unit "memory" 1 3
(and (eq_attr "type" "load") (eq_attr "cpu" "!m88100")) 4 2)
; The fp1 and fplast descriptions currently have no effect.
;(define_function_unit "fp1" 1 1 (eq_attr "fpu" "yes") 1 2)
(define_function_unit "bit" 1 0
(and (eq_attr "type" "bit") (eq_attr "cpu" "!m88100")) 2 2)
(define_function_unit "mem100" 1 0
(and (eq_attr "type" "store,loada") (eq_attr "cpu" "m88100")) 1 0)
(define_function_unit "mem100" 1 0
(and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 0)
(define_function_unit "mem100" 1 0
(and (eq_attr "type" "loadd") (eq_attr "cpu" "m88100")) 3 2
[(eq_attr "type" "load,store,loadd,loada")])
(define_function_unit "mem110" 1 0
(and (eq_attr "type" "load") (eq_attr "cpu" "!m88100")) 3 2)
(define_function_unit "mem110" 1 0
(and (eq_attr "type" "loadd") (eq_attr "cpu" "!m88100")) 3 3
[(eq_attr "type" "load")])
(define_function_unit "mem110" 1 0
(and (eq_attr "type" "loadd") (eq_attr "cpu" "!m88100")) 3 2
[(eq_attr "type" "!load")])
(define_function_unit "mem110" 1 0
(and (eq_attr "type" "store") (eq_attr "cpu" "!m88100")) 0 2)
; The times are adjusted to include fp1 and fplast, but then are further
; adjusted based on the actual generated code. The notation to the right
; is the total latency. A range denotes a group of instructions and/or
; conditions (the extra clock of fplast time with some sequences).
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 2) ; 6-8
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 2) ; 9-10
(define_function_unit "fpmul" 1 4
(and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 2) ; 4
(define_function_unit "fpmul" 1 4
(define_function_unit "fpmul100" 1 0
(and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 0) ; 6-8
(define_function_unit "fpmul100" 1 0
(and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 0) ; 9-10
(define_function_unit "fpmul100" 1 0
(and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 0) ; 4
(define_function_unit "fpmul110" 1 0
(and (eq_attr "type" "imul,spmul,dpmul")
(eq_attr "cpu" "!m88100")) 6 2) ; 3
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 2) ; 5-6
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 2) ; 6-7
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 2) ; 30-31
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 2) ; 60-61
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 2) ; 38
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 6 2) ; 3
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2) ; 3
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 26 2) ; 13
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 46 2) ; 23
(define_function_unit "fpadd" 1 3
(and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 36 2) ; 18
;(define_function_unit "fplast" 1 1 (eq_attr "fpu" "yes") 1 2)
; Describing writeback contention is currently not useful.
;(define_function_unit "writeback" 1 1
; (eq_attr "type" "!store,branch,jump,call") 0 1)
; Describing stores is currently not useful. The suggestion here is that the
; function unit ordering has already been established (writeback is last) and
; that store insns use the units in an unusual order.
;(define_function_unit "writeback" 1 1 (eq_attr "type" "store") 0 1)
;(define_function_unit "memory" 1 3 (eq_attr "type" "store") 1 2)
(eq_attr "cpu" "!m88100")) 5 2) ; 3
(define_function_unit "fpadd100" 1 5
(and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 0) ; 5-6
(define_function_unit "fpadd100" 1 5
(and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 0) ; 6-7
(define_function_unit "fpadd110" 1 0
(and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 5 2) ; 3
(define_function_unit "fpadd110" 1 0
(and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2) ; 1
(define_function_unit "fpadd100" 1 5
(and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 0) ; 30-31
(define_function_unit "fpadd100" 1 5
(and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 0) ; 60-61
(define_function_unit "fpadd100" 1 5
(and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 0) ; 38
(define_function_unit "div" 1 1
(and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 25 2) ; 13
(define_function_unit "div" 1 1
(and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 45 2) ; 23
(define_function_unit "div" 1 1
(and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 35 2) ; 18
;; Superoptimizer sequences
......@@ -1603,7 +1597,7 @@
mov %0,%1
ld.d %0,%1
st.d %1,%0"
[(set_attr "type" "marith,load,store,mov,mov,mov,load,store")])
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
......@@ -1676,7 +1670,7 @@
mov %0,%1
ld.d %0,%1
st.d %1,%0"
[(set_attr "type" "marith,load,store,mov,mov,mov,load,store")])
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=r")
......
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