Skip to content

R
riscv-gcc-1
Commit 84722cca by Christophe Lyon Committed by Christophe Lyon
Options

[ARM/AArch64][testsuite] Add vsubw tests, putting most of the code in common… 

[ARM/AArch64][testsuite] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc.

2015-01-21  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
	vXXXw.inc.

From-SVN: r219938
parent 9ba08321
Showing with 131 additions and 73 deletions
gcc/testsuite/ChangeLog
2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
vXXXw.inc.
2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc 0 → 100644
#define FNNAME1(NAME) exec_ ## NAME
#define FNNAME(NAME) FNNAME1(NAME)
void FNNAME (INSN_NAME) (void)
{
/* Basic test: y=vaddw(x1,x2), then store the result. */
#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
VECT_VAR(vector_res, T1, W2, N) = \
INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
VECT_VAR(vector2, T1, W, N)); \
vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
TEST_VADDW1(INSN, T1, T2, W, W2, N)
DECL_VARIABLE(vector, int, 16, 8);
DECL_VARIABLE(vector, int, 32, 4);
DECL_VARIABLE(vector, int, 64, 2);
DECL_VARIABLE(vector, uint, 16, 8);
DECL_VARIABLE(vector, uint, 32, 4);
DECL_VARIABLE(vector, uint, 64, 2);
DECL_VARIABLE(vector2, int, 8, 8);
DECL_VARIABLE(vector2, int, 16, 4);
DECL_VARIABLE(vector2, int, 32, 2);
DECL_VARIABLE(vector2, uint, 8, 8);
DECL_VARIABLE(vector2, uint, 16, 4);
DECL_VARIABLE(vector2, uint, 32, 2);
DECL_VARIABLE(vector_res, int, 16, 8);
DECL_VARIABLE(vector_res, int, 32, 4);
DECL_VARIABLE(vector_res, int, 64, 2);
DECL_VARIABLE(vector_res, uint, 16, 8);
DECL_VARIABLE(vector_res, uint, 32, 4);
DECL_VARIABLE(vector_res, uint, 64, 2);
clean_results ();
/* Initialize input "vector" from "buffer". */
VLOAD(vector, buffer, q, int, s, 16, 8);
VLOAD(vector, buffer, q, int, s, 32, 4);
VLOAD(vector, buffer, q, int, s, 64, 2);
VLOAD(vector, buffer, q, uint, u, 16, 8);
VLOAD(vector, buffer, q, uint, u, 32, 4);
VLOAD(vector, buffer, q, uint, u, 64, 2);
/* Choose init value arbitrarily. */
VDUP(vector2, , int, s, 8, 8, -13);
VDUP(vector2, , int, s, 16, 4, -14);
VDUP(vector2, , int, s, 32, 2, -16);
VDUP(vector2, , uint, u, 8, 8, 0xf3);
VDUP(vector2, , uint, u, 16, 4, 0xfff1);
VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
/* Execute the tests. */
TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
CHECK_RESULTS (TEST_MSG, "");
}
int main (void)
{
FNNAME (INSN_NAME) ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
......@@ -2,6 +2,9 @@
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define INSN_NAME vaddw
#define TEST_MSG "VADDW"
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
......@@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
0x33333333, 0x33333333 };
#define INSN_NAME vaddw
#define TEST_MSG "VADDW"
#define FNNAME1(NAME) exec_ ## NAME
#define FNNAME(NAME) FNNAME1(NAME)
void FNNAME (INSN_NAME) (void)
{
/* Basic test: y=vaddw(x1,x2), then store the result. */
#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
VECT_VAR(vector_res, T1, W2, N) = \
INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
VECT_VAR(vector2, T1, W, N)); \
vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
TEST_VADDW1(INSN, T1, T2, W, W2, N)
DECL_VARIABLE(vector, int, 16, 8);
DECL_VARIABLE(vector, int, 32, 4);
DECL_VARIABLE(vector, int, 64, 2);
DECL_VARIABLE(vector, uint, 16, 8);
DECL_VARIABLE(vector, uint, 32, 4);
DECL_VARIABLE(vector, uint, 64, 2);
DECL_VARIABLE(vector2, int, 8, 8);
DECL_VARIABLE(vector2, int, 16, 4);
DECL_VARIABLE(vector2, int, 32, 2);
DECL_VARIABLE(vector2, uint, 8, 8);
DECL_VARIABLE(vector2, uint, 16, 4);
DECL_VARIABLE(vector2, uint, 32, 2);
DECL_VARIABLE(vector_res, int, 16, 8);
DECL_VARIABLE(vector_res, int, 32, 4);
DECL_VARIABLE(vector_res, int, 64, 2);
DECL_VARIABLE(vector_res, uint, 16, 8);
DECL_VARIABLE(vector_res, uint, 32, 4);
DECL_VARIABLE(vector_res, uint, 64, 2);
clean_results ();
/* Initialize input "vector" from "buffer". */
VLOAD(vector, buffer, q, int, s, 16, 8);
VLOAD(vector, buffer, q, int, s, 32, 4);
VLOAD(vector, buffer, q, int, s, 64, 2);
VLOAD(vector, buffer, q, uint, u, 16, 8);
VLOAD(vector, buffer, q, uint, u, 32, 4);
VLOAD(vector, buffer, q, uint, u, 64, 2);
/* Choose init value arbitrarily. */
VDUP(vector2, , int, s, 8, 8, -13);
VDUP(vector2, , int, s, 16, 4, -14);
VDUP(vector2, , int, s, 32, 2, -16);
VDUP(vector2, , uint, u, 8, 8, 0xf3);
VDUP(vector2, , uint, u, 16, 4, 0xfff1);
VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
/* Execute the tests. */
TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
CHECK_RESULTS (TEST_MSG, "");
}
int main (void)
{
FNNAME (INSN_NAME) ();
return 0;
}
#include "vXXXw.inc"
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c 0 → 100644
#include <arm_neon.h>
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
#define INSN_NAME vsubw
#define TEST_MSG "VSUBW"
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
0x1, 0x2, 0x3, 0x4 };
VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfefd, 0xfefe, 0xfeff, 0xff00,
0xff01, 0xff02, 0xff03, 0xff04 };
VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffeffff, 0xffff0000,
0xffff0001, 0xffff0002 };
VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffff00000000,
0xffffffff00000001 };
VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
0x33333333, 0x33333333 };
#include "vXXXw.inc"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment