alpha.md (abssf2, absdf2): Disable in IEEE mode.

* alpha.md (abssf2, absdf2): Disable in IEEE mode.
(negsf2, negdf2): Use proper subtract in IEEE mode.

From-SVN: r17440

gcc/ChangeLog

+Thu Jan 22 01:40:52 1998  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.md (abssf2, absdf2): Disable in IEEE mode.
+	(negsf2, negdf2): Use proper subtract in IEEE mode.
+
 Tue Jan 20 09:29:09 1998  Jeffrey A Law  (law@cygnus.com)
 
 	* Makefile.in: Remove more bytecode stuff.

gcc/config/alpha/alpha.md

@@ -1620,24 +1620,40 @@
 (define_insn "abssf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
+  "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
   "cpys $f31,%R1,%0"
   [(set_attr "type" "fcpys")])
 
 (define_insn "absdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
+  "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
   "cpys $f31,%R1,%0"
   [(set_attr "type" "fcpys")])
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
+  "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
   "cpysn %R1,%R1,%0"
   [(set_attr "type" "fadd")])
 
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "sub%,%)%& $f31,%R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP"
+  "sub%,%)%& $f31,%R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
@@ -1646,6 +1662,22 @@
   [(set_attr "type" "fadd")])
 
 (define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "sub%-%)%& $f31,%R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP"
+  "sub%-%)%& $f31,%R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=&f")
 	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]