Bulk ns32k patch from Ian Dall. See ChangeLog for details.

Co-Authored-By: Matthias Pfaller <leo@dachau.marco.de>

From-SVN: r23887

gcc/ChangeLog

+Wed Nov 25 23:32:02 1998  Ian Dall  <Ian.Dall@dsto.defence.gov.au>
+			  Matthias Pfaller  <leo@dachau.marco.de>
+
+	* invoke.texi (Option Summary, NS32K Options): add description
+ 	of NS32K specific options.
+
+	* ns32k.md (tstdf, cmpdf, movdf, truncdfsf2, fixdfqi2, fixdfhi2,
+ 	fixdfsi2, fixunsdfqi2, fixunsdfhi2, fixunsdfsi2, fix_truncdfqi2,
+ 	fix_truncdfhi2, fix_truncdfsi2, adddf3, subdf3, muldf3, divdf3,
+ 	negdf2, absdf2): Use l instead of f since the double class and
+ 	float class are no longer the same.
+	(cmpsi, truncsiqi2, truncsihi2, addsi3, subsi3, mulsi3, umulsidi3,
+ 	divsi3, modsi3, andsi3, iorsi3, xorsi3, negsi2, one_cmplsi2,
+ 	ashlsi3, ashlhi3, ashlqi3, rotlsi3, rotlhi3, rotlqi3, abssi2,...):
+ 	use "g" instead of "rmn" since LEGITIMATE_PIC_OPERAND has been
+ 	fixed.
+	(cmpsi, cmphi, cmpqi): use general_operand instead of
+ 	non_immediate_operand. Removes erroneous assumption that can't
+ 	compare constants.
+	(movsf, movsi, movhi, movqi,...): New register numbering scheme.
+	(movsi, addsi3): Use NS32K_DISPLACEMENT_P instead of hard coded
+ 	constants.
+	(movstrsi, movstrsi1, movstrsi2): completely new block move
+ 	scheme.
+	(...): Patterns to exploit multiply-add instructions.
+	(udivmodsi4, udivmodsi_internal4, udivmodhi4,
+ 	udivmoddihi4_internal, udivmodqi4, udivmoddiqi4_internal): new
+ 	patterns to exploit extended divide insns.
+	(udivsi3, udivhi3, udivqi3): remove since superceded by udivmodsi
+	etc patterns.
+
+	* ns32k.h (FUNCTION_VALUE, LIBCALL_VALUE): Use f0 for complex
+ 	float return values as well as simple scalar floats.
+	(TARGET_32381, TARGET_MULT_ADD, TARGET_SWITCHES):
+ 	support new flag to denote 32381 fpu.
+	(OVERRIDE_OPTIONS): 32381 is a strict superset of 32081.
+	(CONDITIONAL_REGISTER_USAGE): disable extra 32381 registers if not
+ 	compling for 32381.
+	(FIRST_PSEUDO_REGISTER, FIXED_REGISTERS, CALL_USED_REGISTERS,
+ 	REGISTER_NAMES, ADDITIONAL_REGISTER_NAMES, OUTPUT_REGISTER_NAMES,
+ 	REG_ALLOC_ORDER, DBX_REGISTER_NUMBER, R0_REGNUM, F0_REGNUM,
+ 	L1_REGNUM, STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM,
+ 	LONG_FP_REGS_P, ARG_POINTER_REGNUM, reg_class, REG_CLASS_NAMES,
+ 	REG_CLASS_CONTENTS, SUBSET_P,REGNO_REG_CLASS,
+ 	REG_CLASS_FROM_LETTER, FUNCTION_PROLOGUE, FUNCTION_EPILOGUE,
+ 	REGNO_OK_FOR_INDEX_P, FP_REG_P, REG_OK_FOR_INDEX_P,
+ 	REG_OK_FOR_BASE_P, MEM_REG): new register scheme to include 32381
+ 	fpu registers and special register classes for new 32381
+ 	instructions dotf and polyf.
+	(MODES_TIEABLE_P): Allow all integer modes, notably DI and SI, to
+ 	be tieable.
+	(INCOMING_RETURN_ADDR_RTX, RETURN_ADDR_RTX,
+ 	INCOMING_FRAME_SP_OFFSET): New macros in case DWARF support is
+ 	required.
+	(SMALL_REGISTER_CLASSES): Make dependant on -mmult-add option.
+	(MOVE_RATIO): Set to zero because of smart movstrsi implimentation.
+	(REGISTER_MOVE_COST): move code to register_move_cost function for
+	ease of coding and debugging.
+	(CLASS_LIKELY_SPILLED_P): Under new register scheme class
+ 	LONG_FLOAT_REGO is likely spilled but not caught by default
+ 	definition.
+	(CONSTANT_ADDRESS_P, CONSTANT_ADDRESS_NO_LABEL_P): use macro
+ 	instead of hard coded numbers in range check.
+	(ASM_OUTPUT_LABELREF_AS_INT): delete since unused.
+	(...): Add prototypes for functions in ns32k.c but disable because
+	of problems when ns32k.h is included in machine independant files.
+	
+	* ns32k.c: include "system.h", "tree.h", "expr.h", "flags.h".
+	(ns32k_reg_class_contents, regcass_map, ns32k_out_reg_names,
+ 	hard_regno_mode_ok, secondary_reload_class,
+ 	print_operand, print_operand_address): new register scheme to
+ 	include 32381 fpu registers and special register classes for new
+ 	32381 instructions dotf and polyf.
+	(gen_indexed_expr): Make static to keep namespace clean.
+	(check_reg): remove since never called.
+	(move_tail, expand_block_move): helper functions for "movstrsi"
+ 	block move insn.
+	(register_move_cost): Helper function for REGISTER_MOVE_COST macro.
+	Increase cost of moves which go via memory.
+	* netbsd.h (TARGET_DEFAULT): Set (new) 32381 fpu flag.
+	(CPP_PREDEFINES): nolonger predefine "unix".
+
+	* ns32k.md (movsi, movsi, adddi3, subdi3, subsi3, subhi3, subqi3,...):
+ 	Remove erroneous %$. print_operand() can work out from the rtx is
+ 	an immediate prefix is required.
+
+	* ns32k.h (RETURN_POPS_ARGS, VALID_MACHINE_DECL_ATTRIBUTE,
+ 	VALID_MACHINE_TYPE_ATTRIBUTE, COMP_TYPE_ATTRIBUTES,
+ 	SET_DEFAULT_TYPE_ATTRIBUTES): Support for -mrtd calling
+ 	convention.
+	(LEGITIMATE_PIC_OPERAND_P, SYMBOLIC_CONST): Correct handling of
+ 	pic operands.
+
+	* ns32k.c (symbolic_reference_mentioned_p, print_operand):
+	Correct handling of pic operands.
+	(ns32k_valid_decl_attribute_p, ns32k_valid_type_attribute_p,
+ 	ns32k_comp_type_attributes, ns32k_return_pops_args): Support for
+	-mrtd calling convention.
+
 Wed Nov 25 23:42:20 1998  Tom Tromey  <tromey@cygnus.com>
 
 	* gcc.c (option_map): Recognize --output-class-directory.
@@ -13,7 +112,6 @@ Thu Nov 26 18:26:21 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 	too large to be immediate constants.  Also use it to find terms
 	common to initial and final iteration values that can be removed.
 
-
 Thu Nov 26 18:05:04 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 
 	* loop.h (struct loop_info): Define new structure.
@@ -42,7 +140,6 @@ Thu Nov 26 18:05:04 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 	(loop_unroll_factor): Replace global array by element in
 	loop_info structure.
 
-
 Thu Nov 26 17:49:29 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 
 	* loop.c (check_dbra_loop): Update JUMP_LABEL field of jump insn
@@ -87,7 +184,6 @@ Thu Nov 26 15:16:05 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 	(valid_parallel_operands_4, valid_parallel_operands_5,
  	valid_parallel_operands_6): Reject pattern if the register destination
 	of the first set is used as part of an address in the second set.
-	
 
 Thu Nov 26 14:56:32 1998  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 

gcc/README.NS32K

 This file describes the implementation notes of the GNU C Compiler for
 the National Semiconductor 32032 chip (and 32000 family).
 
+Much of this file was obsolete. It described restrictions caused by
+bugs in early versions of of the ns32032 chip and by bugs in sequent
+assemblers and linkers of the time.
+
+Many (all?) of the chip bugs were fixed in later revisions and
+certainly fixed by later chips in the same series (ns32332 and
+ns32532).
+
+Conditional code to support sequent assembler and/or linker restrictions
+has not been removed deliberately, but has probably not been tested in
+a *very* long time.
+
+Support for one sequent assembler bug has *not* been retained.
+It was necessary to say:
+
+	addr _x,rn
+	cmpd _p,rn
+
+rather than:
+
+	cmpd _p,@_x
+
+
+This used to be forced by the use of "rmn" register constraints rather
+than "g". This is bad for other platforms which do not have this
+restraint.
+
+It is likely that there are no Balance 8000's still in operation, but
+if there are and the assembler bug was never fixed then the easiest
+way to run gcc would be to also run gas.
+
+The code required by the sequent assembler is still generated when the
+-fpic flag is in effect and this is forced by the appropriate
+definition of LEGITIMATE_PIC_OPERAND_P. If support for the old sequent
+assembler bug is required, then this could be achieved by adding the
+test from LEGITIMATE_PIC_OPERAND to the GO_IF_LEGITIMATE_ADDRESS
+definition. Of course, this should be conditional on something in the
+sequent.h config file.
+
+The original contents of this file appear below as an historical note.
+SEQUENT_ADDRESS_BUG mentioned below has been replaced by
+INDEX_RATHER_THAN_BASE. Note that merlin.h still defines
+SEQUENT_ADDRESS_BUG even though it is not used anywhere. Since it has
+been like this for a long time, presumably either the
+SEQUENT_ADDRESS_BUG is not required for the merlin, or no one is using
+gcc on the merlin anymore.
+
+HISTORICAL NOTE
+
 The 32032 machine description and configuration file for this compiler
 is, for NS32000 family machine, primarily machine independent.
 However, since this release still depends on vendor-supplied

gcc/config/ns32k/netbsd.h

@@ -24,9 +24,10 @@ Boston, MA 02111-1307, USA.
 
 /* Compile for the floating point unit & 32532 by default;
    Don't assume SB is zero;
-   Don't use bitfield instructions; */
+   Don't use bitfield instructions;
+   FPU is 32381; */
 
-#define TARGET_DEFAULT (1 + 24 + 32 + 64)
+#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256)
 
 /* 32-bit alignment for efficiency */
 
@@ -68,7 +69,7 @@ Boston, MA 02111-1307, USA.
 /* Names to predefine in the preprocessor for this target machine.  */
 
 #undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dns32k -Dns32000 -Dns32532 -D__NetBSD__ -Dpc532 -D__ns32k__ -Asystem(unix) -Asystem(NetBSD) -Acpu(ns32k) -Amachine(ns32k)"
+#define CPP_PREDEFINES "-Dns32k -Dns32000 -Dns32532 -D__NetBSD__ -Dpc532 -D__ns32k__ -D__KPRINTF_ATTRIBUTE__ -Asystem(unix) -Asystem(NetBSD) -Acpu(ns32k) -Amachine(ns32k)"
 
 /* Make gcc agree with <machine/ansi.h> */
 

gcc/invoke.texi

@@ -393,6 +393,11 @@ in the following sections.
 -mprolog-function -mno-prolog-function -mspace
 -mtda=@var{n} -msda=@var{n} -mzda=@var{n}
 -mv850 -mbig-switch
+
+@emph{NS32K Options}
+-m32032 -m32332 -m32532 -m32081 -m32381 -mmult-add -mnomult-add
+-msoft-float -mrtd -mnortd -mregparam -mnoregparam -msb -mnosb
+-mbitfield -mnobitfield -mhimem -mnohimem
 @end smallexample
 
 @item Code Generation Options
@@ -3055,6 +3060,7 @@ that macro, which enables you to change the defaults.
 * System V Options::
 * V850 Options::
 * ARC Options::
+* NS32K Options::
 @end menu
 
 @node M680x0 Options
@@ -5678,6 +5684,121 @@ by default.  This can be overridden with the @code{section} attribute.
 
 @end table
 
+@node NS32K Options
+@subsection NS32K Options
+@cindex NS32K options
+
+These are the @samp{-m} options defined for the 32000 series.  The default
+values for these options depends on which style of 32000 was selected when
+the compiler was configured; the defaults for the most common choices are
+given below.
+
+@table @code
+@item -m32032
+@itemx -m32032
+Generate output for a 32032.  This is the default
+when the compiler is configured for 32032 and 32016 based systems.
+
+@item -m32332
+@itemx -m32332
+Generate output for a 32332.  This is the default
+when the compiler is configured for 32332-based systems.
+
+@item -m32532
+@itemx -m32532
+Generate output for a 32532.  This is the default
+when the compiler is configured for 32532-based systems.
+
+@item -m32081
+Generate output containing 32081 instructions for floating point.
+This is the default for all systems.
+
+@item -m32381
+Generate output containing 32381 instructions for floating point.  This
+also implies @samp{-m32081}. The 32381 is only compatible with the 32332
+and 32532 cpus. This is the default for the pc532-netbsd configuration.
+
+@item -mmulti-add
+Try and generate multiply-add floating point instructions @code{polyF}
+and @code{dotF}. This option is only available if the @samp{-m32381}
+option is in effect. Using these instructions requires changes to to
+register allocation which generally has a negative impact on
+performance.  This option should only be enabled when compiling code
+particularly likely to make heavy use of multiply-add instructions.
+
+@item -mnomulti-add
+Do not try and generate multiply-add floating point instructions
+@code{polyF} and @code{dotF}. This is the default on all platforms.
+
+@item -msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries may not be available.
+
+@item -mnobitfield
+Do not use the bit-field instructions. On some machines it is faster to
+use shifting and masking operations. This is the default for the pc532.
+
+@item -mbitfield
+Do use the bit-field instructions. This is the default for all platforms
+except the pc532.
+
+@item -mrtd
+Use a different function-calling convention, in which functions
+that take a fixed number of arguments return pop their
+arguments on return with the @code{ret} instruction.
+
+This calling convention is incompatible with the one normally
+used on Unix, so you cannot use it if you need to call libraries
+compiled with the Unix compiler.
+
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including @code{printf});
+otherwise incorrect code will be generated for calls to those
+functions.
+
+In addition, seriously incorrect code will result if you call a
+function with too many arguments.  (Normally, extra arguments are
+harmlessly ignored.)
+
+This option takes its name from the 680x0 @code{rtd} instruction.
+
+
+@item -mregparam
+Use a different function-calling convention where the first two arguments
+are passed in registers.
+
+This calling convention is incompatible with the one normally
+used on Unix, so you cannot use it if you need to call libraries
+compiled with the Unix compiler.
+
+@item -mnoregparam
+Do not pass any arguments in registers. This is the default for all
+targets.
+
+@item -msb
+It is OK to use the sb as an index register which is always loaded with
+zero. This is the default for the pc532-netbsd target.
+
+@item -mnosb
+The sb register is not available for use or has not been initialized to
+zero by the run time system. This is the default for all targets except
+the pc532-netbsd. It is also implied whenever @samp{-mhimem} or
+@samp{-fpic} is set.
+
+@item -mhimem
+Many ns32000 series addressing modes use displacements of up to 512MB.
+If an address is above 512MB then displacements from zero can not be used.
+This option causes code to be generated which can be loaded above 512MB.
+This may be useful for operating systems or ROM code.
+
+@item -mnohimem
+Assume code will be loaded in the first 512MB of virtual address space.
+This is the default for all platforms.
+
+
+@end table
+
+
 
 @node Code Gen Options
 @section Options for Code Generation Conventions