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riscv-gcc-1
Commit 83349046 by Segher Boessenkool Committed by Segher Boessenkool
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Split off powerpcspe from rs6000 port 


	* config/powerpcspe: New port.  Files are copied from the rs6000
	port, with "rs6000" in filenames replaced by "powerpcspe".

	* config.gcc (powerpc*-*-*spe*): New.
	(powerpc-*-eabispe*): Use ${cpu_type} instead of hardcoded pathnames.
	(powerpc-*-rtems*spe*): New.
	(powerpc*-*-linux*spe*): New.
	(powerpc-wrs-vxworksspe): New.
	(powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
	(misc flags) [powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
	* config.host (powerpc*-*-*spe*): New.

From-SVN: r248429
parent b6784361
Showing with 4943 additions and 8 deletions
ChangeLog
2017-05-24 Segher Boessenkool <segher@kernel.crashing.org>
* config.gcc (powerpc*-*-*spe*): New.
(powerpc-*-eabispe*): Use ${cpu_type} instead of hardcoded pathnames.
(powerpc-*-rtems*spe*): New.
(powerpc*-*-linux*spe*): New.
(powerpc-wrs-vxworksspe): New.
(powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
(misc flags) [powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
* config.host (powerpc*-*-*spe*): New.
2017-05-19 Martin Liska <mliska@suse.cz>
* configure.ac: Add --enable-werror-always just for
......
gcc/ChangeLog
2017-05-24 Segher Boessenkool <segher@kernel.crashing.org>
* config/powerpcspe: New port. Files are copied from the rs6000
port, with "rs6000" in filenames replaced by "powerpcspe".
2017-05-24 Wilco Dijkstra <wdijkstr@arm.com>
PR rtl-optimization/80754
......
gcc/common/config/powerpcspe/powerpcspe-common.c 0 → 100644
/* Common hooks for IBM RS/6000.
Copyright (C) 1991-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
#include "params.h"
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options rs6000_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
/* Enable -fsched-pressure for first pass instruction scheduling. */
{ OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
/* Implement TARGET_OPTION_INIT_STRUCT. */
static void
rs6000_option_init_struct (struct gcc_options *opts)
{
if (DEFAULT_ABI == ABI_DARWIN)
/* The Darwin libraries never set errno, so we might as well
avoid calling them when that's the only reason we would. */
opts->x_flag_errno_math = 0;
/* Enable section anchors by default. */
if (!TARGET_MACHO)
opts->x_flag_section_anchors = 1;
}
/* Implement TARGET_OPTION_DEFAULT_PARAMS. */
static void
rs6000_option_default_params (void)
{
/* Double growth factor to counter reduced min jump length. */
set_default_param_value (PARAM_MAX_GROW_COPY_BB_INSNS, 16);
}
/* If not otherwise specified by a target, make 'long double' equivalent to
'double'. */
#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
#endif
/* Implement TARGET_HANDLE_OPTION. */
static bool
rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
const struct cl_decoded_option *decoded,
location_t loc)
{
enum fpu_type_t fpu_type = FPU_NONE;
char *p, *q;
size_t code = decoded->opt_index;
const char *arg = decoded->arg;
int value = decoded->value;
switch (code)
{
case OPT_mfull_toc:
opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC;
opts->x_TARGET_NO_FP_IN_TOC = 0;
opts->x_TARGET_NO_SUM_IN_TOC = 0;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
#ifdef TARGET_USES_SYSV4_OPT
/* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
just the same as -mminimal-toc. */
opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
#endif
break;
#ifdef TARGET_USES_SYSV4_OPT
case OPT_mtoc:
/* Make -mtoc behave like -mminimal-toc. */
opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
break;
#endif
#ifdef TARGET_USES_AIX64_OPT
case OPT_maix64:
#else
case OPT_m64:
#endif
opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags
& OPTION_MASK_PPC_GFXOPT);
opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
break;
#ifdef TARGET_USES_AIX64_OPT
case OPT_maix32:
#else
case OPT_m32:
#endif
opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
break;
case OPT_mminimal_toc:
if (value == 1)
{
opts->x_TARGET_NO_FP_IN_TOC = 0;
opts->x_TARGET_NO_SUM_IN_TOC = 0;
}
break;
case OPT_mpowerpc_gpopt:
case OPT_mpowerpc_gfxopt:
break;
case OPT_mdebug_:
p = ASTRDUP (arg);
opts->x_rs6000_debug = 0;
while ((q = strtok (p, ",")) != NULL)
{
unsigned mask = 0;
bool invert;
p = NULL;
if (*q == '!')
{
invert = true;
q++;
}
else
invert = false;
if (! strcmp (q, "all"))
mask = MASK_DEBUG_ALL;
else if (! strcmp (q, "stack"))
mask = MASK_DEBUG_STACK;
else if (! strcmp (q, "arg"))
mask = MASK_DEBUG_ARG;
else if (! strcmp (q, "reg"))
mask = MASK_DEBUG_REG;
else if (! strcmp (q, "addr"))
mask = MASK_DEBUG_ADDR;
else if (! strcmp (q, "cost"))
mask = MASK_DEBUG_COST;
else if (! strcmp (q, "target"))
mask = MASK_DEBUG_TARGET;
else if (! strcmp (q, "builtin"))
mask = MASK_DEBUG_BUILTIN;
else
error_at (loc, "unknown -mdebug-%s switch", q);
if (invert)
opts->x_rs6000_debug &= ~mask;
else
opts->x_rs6000_debug |= mask;
}
break;
#ifdef TARGET_USES_SYSV4_OPT
case OPT_mrelocatable:
if (value == 1)
{
opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
opts->x_TARGET_NO_FP_IN_TOC = 1;
}
break;
case OPT_mrelocatable_lib:
if (value == 1)
{
opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
| OPTION_MASK_MINIMAL_TOC);
opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
| OPTION_MASK_MINIMAL_TOC);
opts->x_TARGET_NO_FP_IN_TOC = 1;
}
else
{
opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE;
}
break;
#endif
case OPT_mabi_altivec:
/* Enabling the AltiVec ABI turns off the SPE ABI. */
opts->x_rs6000_spe_abi = 0;
break;
case OPT_mabi_spe:
opts->x_rs6000_altivec_abi = 0;
break;
case OPT_mlong_double_:
if (value != 64 && value != 128)
{
error_at (loc, "unknown switch -mlong-double-%s", arg);
opts->x_rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE;
return false;
}
break;
case OPT_msingle_float:
if (!TARGET_SINGLE_FPU)
warning_at (loc, 0,
"-msingle-float option equivalent to -mhard-float");
/* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_double_float = 0;
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_mdouble_float:
/* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_single_float = 1;
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_msimple_fpu:
if (!TARGET_SINGLE_FPU)
warning_at (loc, 0, "-msimple-fpu option ignored");
break;
case OPT_mhard_float:
/* -mhard_float implies -msingle-float and -mdouble-float. */
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
break;
case OPT_msoft_float:
/* -msoft_float implies -mnosingle-float and -mnodouble-float. */
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
break;
case OPT_mfpu_:
fpu_type = (enum fpu_type_t) value;
if (fpu_type != FPU_NONE)
{
/* If -mfpu is not none, then turn off SOFT_FLOAT, turn on
HARD_FLOAT. */
opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_xilinx_fpu = 1;
if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL)
opts->x_rs6000_single_float = 1;
if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL)
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
if (fpu_type == FPU_SF_LITE || fpu_type == FPU_DF_LITE)
opts->x_rs6000_simple_fpu = 1;
}
else
{
/* -mfpu=none is equivalent to -msoft-float. */
opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
}
break;
case OPT_mrecip:
opts->x_rs6000_recip_name = (value) ? "default" : "none";
break;
}
return true;
}
/* -fsplit-stack uses a field in the TCB, available with glibc-2.19.
We also allow 2.18 because alignment padding guarantees that the
space is available there too. */
static bool
rs6000_supports_split_stack (bool report,
struct gcc_options *opts ATTRIBUTE_UNUSED)
{
#ifndef TARGET_GLIBC_MAJOR
#define TARGET_GLIBC_MAJOR 0
#endif
#ifndef TARGET_GLIBC_MINOR
#define TARGET_GLIBC_MINOR 0
#endif
/* Note: Can't test DEFAULT_ABI here, it isn't set until later. */
if (TARGET_GLIBC_MAJOR * 1000 + TARGET_GLIBC_MINOR >= 2018
&& TARGET_64BIT
&& TARGET_ELF)
return true;
if (report)
error ("%<-fsplit-stack%> currently only supported on PowerPC64 GNU/Linux with glibc-2.18 or later");
return false;
}
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION rs6000_handle_option
#undef TARGET_OPTION_INIT_STRUCT
#define TARGET_OPTION_INIT_STRUCT rs6000_option_init_struct
#undef TARGET_OPTION_DEFAULT_PARAMS
#define TARGET_OPTION_DEFAULT_PARAMS rs6000_option_default_params
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table
#undef TARGET_SUPPORTS_SPLIT_STACK
#define TARGET_SUPPORTS_SPLIT_STACK rs6000_supports_split_stack
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config.gcc
......@@ -442,6 +442,16 @@ nios2-*-*)
nvptx-*-*)
cpu_type=nvptx
;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
extra_options="${extra_options} g.opt fused-madd.opt powerpcspe/powerpcspe-tables.opt"
;;
powerpc*-*-*)
cpu_type=rs6000
extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h"
......@@ -2372,9 +2382,9 @@ powerpc-*-netbsd*)
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpc-*-eabispe*)
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-spe rs6000/t-ppccomm"
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h ${cpu_type}/sysv4.h ${cpu_type}/eabi.h ${cpu_type}/e500.h ${cpu_type}/eabispe.h"
extra_options="${extra_options} ${cpu_type}/sysv4.opt"
tmake_file="${cpu_type}/t-spe ${cpu_type}/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisimaltivec*)
......@@ -2412,11 +2422,27 @@ powerpc-*-eabi*)
tmake_file="rs6000/t-fprules rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-rtems*spe*)
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h powerpcspe/sysv4.h powerpcspe/eabi.h powerpcspe/e500.h powerpcspe/rtems.h rtems.h"
extra_options="${extra_options} powerpcspe/sysv4.opt"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-rtems powerpcspe/t-ppccomm"
;;
powerpc-*-rtems*)
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-rtems rs6000/t-ppccomm"
;;
powerpc*-*-linux*spe*)
tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h powerpcspe/sysv4.h"
extra_options="${extra_options} powerpcspe/sysv4.opt"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-ppccomm"
extra_objs="$extra_objs powerpcspe-linux.o"
maybe_biarch=
tm_file="${tm_file} powerpcspe/linux.h glibc-stdint.h"
tmake_file="${tmake_file} powerpcspe/t-ppcos powerpcspe/t-linux"
tm_file="${tm_file} powerpcspe/linuxspe.h powerpcspe/e500.h"
default_gnu_indirect_function=yes
;;
powerpc*-*-linux*)
tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
......@@ -2504,6 +2530,13 @@ powerpc*-*-linux*)
;;
esac
;;
powerpc-wrs-vxworksspe)
tm_file="${tm_file} elfos.h freebsd-spec.h powerpcspe/sysv4.h"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-ppccomm powerpcspe/t-vxworks"
extra_options="${extra_options} powerpcspe/sysv4.opt"
extra_headers=ppc-asm.h
tm_file="${tm_file} vx-common.h vxworks.h powerpcspe/vxworks.h powerpcspe/e500.h"
;;
powerpc-wrs-vxworks|powerpc-wrs-vxworksae|powerpc-wrs-vxworksmils)
tm_file="${tm_file} elfos.h freebsd-spec.h rs6000/sysv4.h"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-ppccomm rs6000/t-vxworks"
......@@ -3060,7 +3093,7 @@ i[34567]86-*-* | x86_64-*-*)
tmake_file="${tmake_file} i386/t-gmm_malloc i386/t-i386"
;;
powerpc*-*-* | rs6000-*-*)
tm_file="${tm_file} rs6000/option-defaults.h"
tm_file="${tm_file} ${cpu_type}/option-defaults.h"
esac
# Build mkoffload tool
......@@ -4554,10 +4587,10 @@ case ${target} in
then
target_cpu_default2="\\\"$with_cpu\\\""
fi
out_file=rs6000/rs6000.c
c_target_objs="${c_target_objs} rs6000-c.o"
cxx_target_objs="${cxx_target_objs} rs6000-c.o"
tmake_file="rs6000/t-rs6000 ${tmake_file}"
out_file="${cpu_type}/${cpu_type}.c"
c_target_objs="${c_target_objs} ${cpu_type}-c.o"
cxx_target_objs="${cxx_target_objs} ${cpu_type}-c.o"
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
;;
sh[123456ble]*-*-* | sh-*-*)
......
gcc/config.host
......@@ -144,6 +144,10 @@ case ${host} in
rs6000-*-* \
| powerpc*-*-* )
case ${target} in
powerpc*-*-*spe*)
host_extra_gcc_objs="driver-powerpcspe.o"
host_xmake_file="${host_xmake_file} powerpcspe/x-powerpcspe"
;;
rs6000-*-* \
| powerpc*-*-* )
host_extra_gcc_objs="driver-rs6000.o"
......
gcc/config/powerpcspe/40x.md 0 → 100644
;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc40x,ppc40xiu")
(define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
(define_cpu_unit "iu_40x" "ppc40xiu")
;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
;; Embedded PowerPC controller
;; In-order execution
;; Max issue two insns/cycle (includes one branch)
(define_insn_reservation "ppc403-load" 2
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x")
(define_insn_reservation "ppc403-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc405"))
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
(and (ior (eq_attr "type" "halfmul")
(and (eq_attr "type" "mul")
(eq_attr "size" "8")))
(eq_attr "cpu" "ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-idiv" 33
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x*33")
(define_insn_reservation "ppc403-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc403-cr" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
(and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")
gcc/config/powerpcspe/440.md 0 → 100644
;; Scheduling description for IBM PowerPC 440 processor.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; PPC440 Embedded PowerPC controller
;; dual issue
;; i_pipe - complex integer / compare / branch
;; j_pipe - simple integer arithmetic
;; l_pipe - load-store
;; f_pipe - floating point arithmetic
(define_automaton "ppc440_core,ppc440_apu")
(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
(define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
(and (ior (eq_attr "type" "halfmul")
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-idiv" 34
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe*33")
(define_insn_reservation "ppc440-branch" 1
(and (eq_attr "type" "branch,jmpreg,isync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
(and (ior (eq_attr "type" "cmp,cr_logical,delayed_cr,mfcr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-fpcompare" 3 ; 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
(define_insn_reservation "ppc440-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*15")
(define_insn_reservation "ppc440-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*29")
(define_insn_reservation "ppc440-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
gcc/config/powerpcspe/476.h 0 → 100644
/* Enable IBM PowerPC 476 support.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Peter Bergner (bergner@vnet.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#undef TARGET_LINK_STACK
#define TARGET_LINK_STACK (rs6000_link_stack)
#undef SET_TARGET_LINK_STACK
#define SET_TARGET_LINK_STACK(X) do { TARGET_LINK_STACK = (X); } while (0)
#undef TARGET_ASM_CODE_END
#define TARGET_ASM_CODE_END rs6000_code_end
gcc/config/powerpcspe/476.md 0 → 100644
;; Scheduling description for IBM PowerPC 476 processor.
;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
;; Contributed by Peter Bergner (bergner@vnet.ibm.com).
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; PPC476 Embedded PowerPC controller
;; 3 issue (476) / 4 issue (476fp)
;;
;; i_pipe - complex integer / compare
;; lj_pipe - load-store / simple integer arithmetic
;; b_pipe - branch pipe
;; f_pipe - floating point arithmetic
(define_automaton "ppc476_core,ppc476_apu")
(define_cpu_unit "ppc476_i_pipe,ppc476_lj_pipe,ppc476_b_pipe" "ppc476_core")
(define_cpu_unit "ppc476_issue_fp,ppc476_f_pipe" "ppc476_apu")
(define_cpu_unit "ppc476_issue_0,ppc476_issue_1,ppc476_issue_2" "ppc476_core")
(define_reservation "ppc476_issue" "ppc476_issue_0|ppc476_issue_1|ppc476_issue_2")
(define_reservation "ppc476_issue2" "ppc476_issue_0+ppc476_issue_1\
|ppc476_issue_0+ppc476_issue_2\
|ppc476_issue_1+ppc476_issue_2")
(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2")
(define_insn_reservation "ppc476-load" 4
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-store" 4
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpstore" 4
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-complex-integer" 1
(and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
(and (eq_attr "type" "mul,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-idiv" 11
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe*11")
(define_insn_reservation "ppc476-branch" 1
(and (eq_attr "type" "branch,jmpreg")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_b_pipe")
(define_insn_reservation "ppc476-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc476"))
"ppc476_issue2,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc476"))
"ppc476_issue3,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpcompare" 6
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc476"))
"ppc476_issue+ppc476_issue_fp,\
ppc476_f_pipe+ppc476_i_pipe")
(define_insn_reservation "ppc476-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe")
(define_insn_reservation "ppc476-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,
ppc476_f_pipe*19")
(define_insn_reservation "ppc476-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe*33")
gcc/config/powerpcspe/476.opt 0 → 100644
; IBM PowerPC 476 options.
;
; Copyright (C) 2011-2017 Free Software Foundation, Inc.
; Contributed by Peter Bergner (bergner@vnet.ibm.com)
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
mpreserve-link-stack
Target Var(rs6000_link_stack) Init(-1) Save
Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses.
gcc/config/powerpcspe/601.md 0 → 100644
;; Scheduling description for PowerPC 601 processor.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc601,ppc601fp")
(define_cpu_unit "iu_ppc601" "ppc601")
(define_cpu_unit "fpu_ppc601" "ppc601fp")
(define_cpu_unit "bpu_ppc601" "ppc601")
;; PPC601 32-bit IU, FPU, BPU
(define_insn_reservation "ppc601-load" 2
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-store" 2
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc601"))
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
(and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,isel")
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*5")
(define_insn_reservation "ppc601-idiv" 36
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*36")
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601,nothing,bpu_ppc601")
(define_insn_reservation "ppc601-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc601"))
"(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601")
(define_insn_reservation "ppc601-fp" 4
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601")
(define_insn_reservation "ppc601-dmul" 5
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*2")
(define_insn_reservation "ppc601-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*17")
(define_insn_reservation "ppc601-ddiv" 31
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*31")
(define_insn_reservation "ppc601-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-mtcr" 4
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-crlogical" 4
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc601"))
"bpu_ppc601")
(define_insn_reservation "ppc601-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc601"))
"bpu_ppc601")
gcc/config/powerpcspe/603.md 0 → 100644
;; Scheduling description for PowerPC 603 processor.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc603,ppc603fp")
(define_cpu_unit "iu_603" "ppc603")
(define_cpu_unit "fpu_603" "ppc603fp")
(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 2 insns per cycle.
;; The PPC603e user's manual recommends that to reduce branch mispredictions,
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them; separation by more than 9 insns ensures that the CR
;; bits will be immediately available for execution.
;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; CR insns get executed in the SRU. Not modelled.
(define_insn_reservation "ppc603-load" 2
(and (eq_attr "type" "load,load_l")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc603"))
"lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-storec" 8
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
(define_insn_reservation "ppc603-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603")
(define_insn_reservation "ppc603-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603,iu_603")
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-imul2" 2
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-idiv" 37
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc603"))
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
(define_insn_reservation "ppc603-fpcompare" 3
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc603"))
"(fpu_603+iu_603*2),bpu_603")
(define_insn_reservation "ppc603-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc603"))
"fpu_603")
(define_insn_reservation "ppc603-dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc603"))
"fpu_603*2")
; Divides are not pipelined
(define_insn_reservation "ppc603-sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc603"))
"fpu_603*18")
(define_insn_reservation "ppc603-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc603"))
"fpu_603*33")
(define_insn_reservation "ppc603-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-mfjmpr" 2
(and (eq_attr "type" "mfjmpr,isync,sync")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc603"))
"bpu_603")
gcc/config/powerpcspe/6xx.md 0 → 100644
;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
;; and PowerPC 630 processors.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
(define_cpu_unit "fpu_6xx" "ppc6xxfp")
(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
;; MCIU used for imul/idiv and moves from/to spr
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; Max issue 4 insns/clock cycle
;; PPC604e is PPC604 with larger caches and a CRU. In the 604
;; the CR logical operations are handled in the BPU.
;; In the 604e, the CRU shares bus with BPU so only one condition
;; register or branch insn can be issued per clock. Not modelled.
;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
;; Max issue 4 insns/clock cycle
;; Out-of-order execution, in-order completion
;; No following instruction can dispatch in the same cycle as a branch
;; instruction. Not modelled. This is no problem if RCSP is not
;; enabled since the scheduler stops a schedule when it gets to a branch.
;; Four insns can be dispatched per cycle.
(define_insn_reservation "ppc604-load" 2
(and (eq_attr "type" "load")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-llsc" 3
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc604,ppc604e"))
"lsu_6xx")
(define_insn_reservation "ppc630-llsc" 4
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul2" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul3" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "8")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-lmul" 7
(and (eq_attr "type" "mul")
(eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*5")
(define_insn_reservation "ppc604-idiv" 20
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc604,ppc604e"))
"mciu_6xx*19")
(define_insn_reservation "ppc620-idiv" 37
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc620"))
"mciu_6xx*36")
(define_insn_reservation "ppc630-idiv" 21
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc630"))
"mciu_6xx*20")
(define_insn_reservation "ppc620-ldiv" 37
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
; FPU PPC604{,e},PPC620
(define_insn_reservation "ppc604-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
(define_insn_reservation "ppc604-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
(define_insn_reservation "ppc604-dmul" 3
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
; Divides are not pipelined
(define_insn_reservation "ppc604-sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx*18")
(define_insn_reservation "ppc604-ddiv" 32
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx*32")
(define_insn_reservation "ppc620-ssqrt" 31
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc620"))
"fpu_6xx*31")
(define_insn_reservation "ppc620-dsqrt" 31
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc620"))
"fpu_6xx*31")
; 2xFPU PPC630
(define_insn_reservation "ppc630-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx|fpu2_6xx")
(define_insn_reservation "ppc630-fp" 3
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx|fpu2_6xx")
(define_insn_reservation "ppc630-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*17|fpu2_6xx*17")
(define_insn_reservation "ppc630-ddiv" 21
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*21|fpu2_6xx*21")
(define_insn_reservation "ppc630-ssqrt" 18
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*18|fpu2_6xx*18")
(define_insn_reservation "ppc630-dsqrt" 25
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*25|fpu2_6xx*25")
(define_insn_reservation "ppc604-mfcr" 3
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-mtcr" 2
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604"))
"bpu_6xx")
(define_insn_reservation "ppc604e-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
"cru_6xx")
(define_insn_reservation "ppc604-mtjmpr" 2
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"mciu_6xx")
(define_insn_reservation "ppc630-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"bpu_6xx")
(define_insn_reservation "ppc604-isync" 0
(and (eq_attr "type" "isync")
(eq_attr "cpu" "ppc604,ppc604e"))
"bpu_6xx")
(define_insn_reservation "ppc630-isync" 6
(and (eq_attr "type" "isync")
(eq_attr "cpu" "ppc620,ppc630"))
"bpu_6xx")
(define_insn_reservation "ppc604-sync" 35
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc604,ppc604e"))
"lsu_6xx")
(define_insn_reservation "ppc630-sync" 26
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc620,ppc630"))
"lsu_6xx")
gcc/config/powerpcspe/7450.md 0 → 100644
;; Scheduling description for Motorola PowerPC 7450 processor.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
(define_cpu_unit "mciu_7450" "ppc7450mciu")
(define_cpu_unit "fpu_7450" "ppc7450fp")
(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
;; IU1,IU2,IU3 can perform all integer operations
;; MCIU performs imul and idiv, cr logical, SPR moves
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; It also has 4 vector units, one for each type of vector instruction.
;; However, we can only dispatch 2 instructions per cycle.
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; In-order execution
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 3 insns per cycle.
(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
(define_insn_reservation "ppc7450-load" 3
(and (eq_attr "type" "load,vecload")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-store" 3
(and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450*3")
(define_insn_reservation "ppc7450-llsc" 3
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-sync" 35
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
(define_insn_reservation "ppc7450-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-idiv" 23
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc7450-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
(define_insn_reservation "ppc7450-fp" 5
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
; Divides are not pipelined
(define_insn_reservation "ppc7450-sdiv" 21
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450*21")
(define_insn_reservation "ppc7450-ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450*35")
(define_insn_reservation "ppc7450-mfcr" 2
(and (eq_attr "type" "mfcr,mtcr")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-crlogical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-mtjmpr" 2
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc7450"))
"nothing,bpu_7450")
;; Altivec
(define_insn_reservation "ppc7450-vecsimple" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
(define_insn_reservation "ppc7450-veccomplex" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-veccmp" 2
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-vecfloat" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecflt_7450")
(define_insn_reservation "ppc7450-vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecperm_7450")
gcc/config/powerpcspe/750cl.h 0 → 100644
/* Enable 750cl paired single support.
Copyright (C) 2007-2017 Free Software Foundation, Inc.
Contributed by Revital Eres (eres@il.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#undef TARGET_PAIRED_FLOAT
#define TARGET_PAIRED_FLOAT rs6000_paired_float
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "-m750cl"
gcc/config/powerpcspe/7xx.md 0 → 100644
;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors.
;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc7xx,ppc7xxfp")
(define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx")
(define_cpu_unit "fpu_7xx" "ppc7xxfp")
(define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx")
(define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx")
(define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx")
;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU
;; IU1 can perform all integer operations
;; IU2 can perform all integer operations except imul and idiv
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; In-order execution
;; The PPC750 user's manual recommends that to reduce branch mispredictions,
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them. There is no advantage have more than 10 cycles
;; of separation.
;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 2 insns per cycle.
(define_reservation "ppc750_du" "du1_7xx|du2_7xx")
(define_reservation "ppc7400_vec_du" "vdu_7xx")
(define_insn_reservation "ppc750-load" 2
(and (eq_attr "type" "load,fpload,vecload,load_l")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-store" 2
(and (eq_attr "type" "store,fpstore,vecstore")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-storec" 8
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
(define_insn_reservation "ppc750-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*2")
(define_insn_reservation "ppc750-imul3" 2
(and (eq_attr "type" "mul")
(eq_attr "size" "8")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-idiv" 19
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
(define_insn_reservation "ppc750-fpcompare" 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc750"))
"ppc750_du,fpu_7xx*2")
(define_insn_reservation "ppc7400-dmul" 3
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,fpu_7xx")
; Divides are not pipelined
(define_insn_reservation "ppc750-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx*17")
(define_insn_reservation "ppc750-ddiv" 31
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx*31")
(define_insn_reservation "ppc750-mfcr" 2
(and (eq_attr "type" "mfcr,mtcr")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-crlogical" 3
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-mtjmpr" 2
(and (eq_attr "type" "mtjmpr,isync,sync")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,bpu_7xx")
;; Altivec
(define_insn_reservation "ppc7400-vecsimple" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-veccomplex" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-vecfloat" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,vecperm_7xx")
gcc/config/powerpcspe/a2.md 0 → 100644
;; Scheduling description for PowerPC A2 processors.
;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppca2")
;; CPU units
;; The multiplier pipeline.
(define_cpu_unit "mult" "ppca2")
;; The auxiliary processor unit (FP/vector unit).
(define_cpu_unit "axu" "ppca2")
;; D.4.6
;; Some peculiarities for certain SPRs
(define_insn_reservation "ppca2-mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppca2"))
"nothing")
(define_insn_reservation "ppca2-mfjmpr" 5
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppca2"))
"nothing")
(define_insn_reservation "ppca2-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppca2"))
"nothing")
;; D.4.8
(define_insn_reservation "ppca2-imul" 1
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16,32")
(eq_attr "cpu" "ppca2"))
"nothing")
;; FIXME: latency and multiplier reservation for 64-bit multiply?
(define_insn_reservation "ppca2-lmul" 6
(and (eq_attr "type" "mul")
(eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*3")
;; D.4.9
(define_insn_reservation "ppca2-idiv" 32
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppca2"))
"mult*32")
(define_insn_reservation "ppca2-ldiv" 65
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*65")
;; D.4.13
(define_insn_reservation "ppca2-load" 5
(and (eq_attr "type" "load")
(eq_attr "cpu" "ppca2"))
"nothing")
;; D.8.1
(define_insn_reservation "ppca2-fp" 6
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.4
(define_insn_reservation "ppca2-fp-load" 6
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.5
(define_insn_reservation "ppca2-fp-store" 2
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.6
(define_insn_reservation "ppca2-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.7
;;
;; Instructions from the same thread succeeding the floating-point
;; divide cannot be executed until the floating-point divide has
;; completed. Since there is nothing else we can do, this thread will
;; just have to stall.
(define_insn_reservation "ppca2-ddiv" 72
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppca2"))
"axu")
(define_insn_reservation "ppca2-sdiv" 59
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.8
;;
;; Instructions from the same thread succeeding the floating-point
;; divide cannot be executed until the floating-point divide has
;; completed. Since there is nothing else we can do, this thread will
;; just have to stall.
(define_insn_reservation "ppca2-dsqrt" 69
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppca2"))
"axu")
(define_insn_reservation "ppca2-ssqrt" 65
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppca2"))
"axu")
gcc/config/powerpcspe/aix-stdint.h 0 → 100644
/* Definitions for <stdint.h> types on systems using AIX.
Copyright (C) 2009-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define SIG_ATOMIC_TYPE "int"
#define INT8_TYPE "signed char"
#define INT16_TYPE "short int"
#define INT32_TYPE "int"
#define INT64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT8_TYPE "unsigned char"
#define UINT16_TYPE "short unsigned int"
#define UINT32_TYPE "unsigned int"
#define UINT64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INT_LEAST8_TYPE "signed char"
#define INT_LEAST16_TYPE "short int"
#define INT_LEAST32_TYPE "int"
#define INT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT_LEAST8_TYPE "unsigned char"
#define UINT_LEAST16_TYPE "short unsigned int"
#define UINT_LEAST32_TYPE "unsigned int"
#define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INT_FAST8_TYPE "signed char"
#define INT_FAST16_TYPE "short int"
#define INT_FAST32_TYPE "int"
#define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT_FAST8_TYPE "unsigned char"
#define UINT_FAST16_TYPE "short unsigned int"
#define UINT_FAST32_TYPE "unsigned int"
#define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INTPTR_TYPE "long int"
#define UINTPTR_TYPE "long unsigned int"
gcc/config/powerpcspe/aix43.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX version 4.3.
Copyright (C) 1998-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{!mpowerpc64: %(asm_default)} \
%{mpowerpc64: -mppc64}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
%{ansi: -D_ANSI_C_SOURCE}\
%{maix64: -D__64BIT__}\
%{mpe: -I%R/usr/lpp/ppe.poe/include}\
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "mcpu=common" }
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-L%R/usr/lib/threads -lpthreads -lc_r %R/usr/lib/libc.a}\
%{!pthread:-lc}"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX 4.3 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
/* The IBM AIX 4.x assembler doesn't support forward references in
.set directives. We handle this by deferring the output of .set
directives to the end of the compilation unit. */
#define TARGET_DEFERRED_OUTPUT_DEFS(DECL,TARGET) true
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
#define TARGET_AIX_VERSION 43
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
gcc/config/powerpcspe/aix51.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.
Copyright (C) 2001-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{!mpowerpc64: %(asm_default)} \
%{mpowerpc64: -mppc64}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m620} \
%{mcpu=G5: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "mcpu=common" }
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 51
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
gcc/config/powerpcspe/aix52.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.2.
Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{!mpowerpc64: %(asm_default)}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=power5: -m620} \
%{mcpu=power5+: -m620} \
%{mcpu=power6: -m620} \
%{mcpu=power6x: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m620} \
%{mcpu=G5: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER4
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 52
gcc/config/powerpcspe/aix53.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.3.
Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER5
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER5
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 53
gcc/config/powerpcspe/aix61.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V6.1.
Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
TARGET_NO_FP_IN_TOC = 0; \
TARGET_NO_SUM_IN_TOC = 0; \
} \
if (rs6000_current_cmodel == CMODEL_MEDIUM) \
{ \
rs6000_current_cmodel = CMODEL_LARGE; \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970} \
%{mvsx: %{!mcpu*: -mpwr6}} \
-many"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpwr4"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
builtin_define ("_AIX61"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE -D__COMPATMATH__ \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
/* AIX 6.1 kernel and assembler have necessary support for Altivec and VSX. */
#undef OS_MISSING_ALTIVEC
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}\
%{shared:crtcxa_s%O%s;:crtcxa%O%s} crtdbase%O%s"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* Large TOC Support */
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 61
gcc/config/powerpcspe/aix64.opt 0 → 100644
; Options for the 64-bit flavor of AIX.
;
; Copyright (C) 2005-2017 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
maix64
Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
Compile for 64-bit pointers.
maix32
Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
Compile for 32-bit pointers.
mcmodel=
Target RejectNegative Joined Enum(rs6000_cmodel) Var(rs6000_current_cmodel)
Select code model.
Enum
Name(rs6000_cmodel) Type(enum rs6000_cmodel)
Known code models (for use with the -mcmodel= option):
EnumValue
Enum(rs6000_cmodel) String(small) Value(CMODEL_SMALL)
EnumValue
Enum(rs6000_cmodel) String(medium) Value(CMODEL_MEDIUM)
EnumValue
Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE)
mpe
Target Report RejectNegative Var(internal_nothing_1) Save
Support message passing with the Parallel Environment.
posix
Driver
pthread
Driver
gcc/config/powerpcspe/aix71.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V7.1.
Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
TARGET_NO_FP_IN_TOC = 0; \
TARGET_NO_SUM_IN_TOC = 0; \
} \
if (rs6000_current_cmodel == CMODEL_MEDIUM) \
{ \
rs6000_current_cmodel = CMODEL_LARGE; \
} \
} while (0);
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970} \
%{mvsx: %{!mcpu*: -mpwr6}} \
-many"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpwr4"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
builtin_define ("_AIX61"); \
builtin_define ("_AIX71"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE -D__COMPATMATH__ \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
/* AIX 7.1 kernel and assembler have necessary support for Altivec and VSX. */
#undef OS_MISSING_ALTIVEC
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s;:%{p:mcrt0_64%O%s;:crt0_64%O%s}};:\
%{pthread:%{pg:gcrt0_r%O%s;:%{p:mcrt0_r%O%s;:crt0_r%O%s}};:\
%{pg:gcrt0%O%s;:%{p:mcrt0%O%s;:crt0%O%s}}}}}\
%{shared:crtcxa_s%O%s;:crtcxa%O%s} crtdbase%O%s"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* Large TOC Support */
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 71
/* AIX 7.1 supports DWARF3 debugging, but XCOFF remains the default. */
#define DWARF2_DEBUGGING_INFO 1
#define PREFERRED_DEBUGGING_TYPE XCOFF_DEBUG
#define DEBUG_INFO_SECTION "0x10000"
#define DEBUG_LINE_SECTION "0x20000"
#define DEBUG_PUBNAMES_SECTION "0x30000"
#define DEBUG_PUBTYPES_SECTION "0x40000"
#define DEBUG_ARANGES_SECTION "0x50000"
#define DEBUG_ABBREV_SECTION "0x60000"
#define DEBUG_STR_SECTION "0x70000"
#define DEBUG_RANGES_SECTION "0x80000"
#define DEBUG_LOC_SECTION "0x90000"
#define DEBUG_FRAME_SECTION "0xA0000"
#define DEBUG_MACINFO_SECTION "0xB0000"
#define DEBUG_MACRO_SECTION "0xB0000"
gcc/config/powerpcspe/altivec.md 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/powerpcspe/biarch64.h 0 → 100644
/* Definitions of target machine for GNU compiler, for 32/64 bit powerpc.
Copyright (C) 2003-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specify this in a cover file to provide bi-architecture (32/64) support. */
#define RS6000_BI_ARCH 1
gcc/config/powerpcspe/bmi2intrin.h 0 → 100644
/* Copyright (C) 2011-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This header is distributed to simplify porting x86_64 code that
makes explicit use of Intel intrinsics to powerpc64le.
It is the user's responsibility to determine if the results are
acceptable and make additional changes as necessary.
Note that much code that uses Intel intrinsics can be rewritten in
standard C or GNU C extensions, which are more portable and better
optimized across multiple targets. */
#if !defined _X86INTRIN_H_INCLUDED
# error "Never use <bmi2intrin.h> directly; include <x86intrin.h> instead."
#endif
#ifndef _BMI2INTRIN_H_INCLUDED
#define _BMI2INTRIN_H_INCLUDED
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bzhi_u32 (unsigned int __X, unsigned int __Y)
{
return ((__X << (32 - __Y)) >> (32 - __Y));
}
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mulx_u32 (unsigned int __X, unsigned int __Y, unsigned int *__P)
{
unsigned long long __res = (unsigned long long) __X * __Y;
*__P = (unsigned int) (__res >> 32);
return (unsigned int) __res;
}
#ifdef __PPC64__
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bzhi_u64 (unsigned long long __X, unsigned long long __Y)
{
return ((__X << (64 - __Y)) >> (64 - __Y));
}
/* __int128 requires base 64-bit. */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mulx_u64 (unsigned long long __X, unsigned long long __Y,
unsigned long long *__P)
{
unsigned __int128 __res = (unsigned __int128) __X * __Y;
*__P = (unsigned long long) (__res >> 64);
return (unsigned long long) __res;
}
#ifdef _ARCH_PWR7
/* popcount and bpermd require power7 minimum. */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pdep_u64 (unsigned long long __X, unsigned long long __M)
{
unsigned long result = 0x0UL;
const unsigned long mask = 0x8000000000000000UL;
unsigned long m = __M;
unsigned long c, t;
unsigned long p;
/* The pop-count of the mask gives the number of the bits from
source to process. This is also needed to shift bits from the
source into the correct position for the result. */
p = 64 - __builtin_popcountl (__M);
/* The loop is for the number of '1' bits in the mask and clearing
each mask bit as it is processed. */
while (m != 0)
{
c = __builtin_clzl (m);
t = __X << (p - c);
m ^= (mask >> c);
result |= (t & (mask >> c));
p++;
}
return (result);
}
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pext_u64 (unsigned long long __X, unsigned long long __M)
{
unsigned long p = 0x4040404040404040UL; // initial bit permute control
const unsigned long mask = 0x8000000000000000UL;
unsigned long m = __M;
unsigned long c;
unsigned long result;
/* if the mask is constant and selects 8 bits or less we can use
the Power8 Bit permute instruction. */
if (__builtin_constant_p (__M) && (__builtin_popcountl (__M) <= 8))
{
/* Also if the pext mask is constant, then the popcount is
constant, we can evaluate the following loop at compile
time and use a constant bit permute vector. */
for (long i = 0; i < __builtin_popcountl (__M); i++)
{
c = __builtin_clzl (m);
p = (p << 8) | c;
m ^= (mask >> c);
}
result = __builtin_bpermd (p, __X);
}
else
{
p = 64 - __builtin_popcountl (__M);
result = 0;
/* We could a use a for loop here, but that combined with
-funroll-loops can expand to a lot of code. The while
loop avoids unrolling and the compiler commons the xor
from clearing the mask bit with the (m != 0) test. The
result is a more compact loop setup and body. */
while (m != 0)
{
unsigned long t;
c = __builtin_clzl (m);
t = (__X & (mask >> c)) >> (p - c);
m ^= (mask >> c);
result |= (t);
p++;
}
}
return (result);
}
/* these 32-bit implementations depend on 64-bit pdep/pext
which depend on _ARCH_PWR7. */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pdep_u32 (unsigned int __X, unsigned int __Y)
{
return _pdep_u64 (__X, __Y);
}
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pext_u32 (unsigned int __X, unsigned int __Y)
{
return _pext_u64 (__X, __Y);
}
#endif /* _ARCH_PWR7 */
#endif /* __PPC64__ */
#endif /* _BMI2INTRIN_H_INCLUDED */
gcc/config/powerpcspe/bmiintrin.h 0 → 100644
/* Copyright (C) 2010-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This header is distributed to simplify porting x86_64 code that
makes explicit use of Intel intrinsics to powerpc64le.
It is the user's responsibility to determine if the results are
acceptable and make additional changes as necessary.
Note that much code that uses Intel intrinsics can be rewritten in
standard C or GNU C extensions, which are more portable and better
optimized across multiple targets. */
#if !defined _X86INTRIN_H_INCLUDED
# error "Never use <bmiintrin.h> directly; include <x86intrin.h> instead."
#endif
#ifndef _BMIINTRIN_H_INCLUDED
#define _BMIINTRIN_H_INCLUDED
extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u16 (unsigned short __X)
{
return __builtin_ctz (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__andn_u32 (unsigned int __X, unsigned int __Y)
{
return (~__X & __Y);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bextr_u32 (unsigned int __X, unsigned int __P, unsigned int __L)
{
return ((__X << (32 - (__L + __P))) >> (32 - __L));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bextr_u32 (unsigned int __X, unsigned int __Y)
{
unsigned int __P, __L;
__P = __Y & 0xFF;
__L = (__Y >> 8) & 0xFF;
return (_bextr_u32 (__X, __P, __L));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsi_u32 (unsigned int __X)
{
return (__X & -__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsi_u32 (unsigned int __X)
{
return __blsi_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsmsk_u32 (unsigned int __X)
{
return (__X ^ (__X - 1));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsmsk_u32 (unsigned int __X)
{
return __blsmsk_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsr_u32 (unsigned int __X)
{
return (__X & (__X - 1));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsr_u32 (unsigned int __X)
{
return __blsr_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u32 (unsigned int __X)
{
return __builtin_ctz (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_tzcnt_u32 (unsigned int __X)
{
return __builtin_ctz (__X);
}
/* use the 64-bit shift, rotate, and count leading zeros instructions
for long long. */
#ifdef __PPC64__
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__andn_u64 (unsigned long long __X, unsigned long long __Y)
{
return (~__X & __Y);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bextr_u64 (unsigned long long __X, unsigned int __P, unsigned int __L)
{
return ((__X << (64 - (__L + __P))) >> (64 - __L));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bextr_u64 (unsigned long long __X, unsigned long long __Y)
{
unsigned int __P, __L;
__P = __Y & 0xFF;
__L = (__Y & 0xFF00) >> 8;
return (_bextr_u64 (__X, __P, __L));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsi_u64 (unsigned long long __X)
{
return __X & -__X;
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsi_u64 (unsigned long long __X)
{
return __blsi_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsmsk_u64 (unsigned long long __X)
{
return (__X ^ (__X - 1));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsmsk_u64 (unsigned long long __X)
{
return __blsmsk_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsr_u64 (unsigned long long __X)
{
return (__X & (__X - 1));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsr_u64 (unsigned long long __X)
{
return __blsr_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u64 (unsigned long long __X)
{
return __builtin_ctzll (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_tzcnt_u64 (unsigned long long __X)
{
return __builtin_ctzll (__X);
}
#endif /* __PPC64__ */
#endif /* _BMIINTRIN_H_INCLUDED */
gcc/config/powerpcspe/crypto.md 0 → 100644
;; Cryptographic instructions added in ISA 2.07
;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; NOTE: Although this file contains all the instructions from
;; section 5.11 of ISA 2.07, only those in sections 5.11.1 and
;; 5.11.2 are in Category:Vector.Crypto. Those are the only
;; ones controlled by -m[no-]crypto.
;; FIXME: The builtin names for the instructions in this file
;; are likely to be deprecated in favor of other names to be
;; agreed upon with the XL compilers and LLVM.
(define_c_enum "unspec"
[UNSPEC_VCIPHER
UNSPEC_VNCIPHER
UNSPEC_VCIPHERLAST
UNSPEC_VNCIPHERLAST
UNSPEC_VSBOX
UNSPEC_VSHASIGMA
UNSPEC_VPERMXOR
UNSPEC_VPMSUM])
;; Iterator for VPMSUM/VPERMXOR
(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])
(define_mode_attr CR_char [(V16QI "b")
(V8HI "h")
(V4SI "w")
(V2DI "d")])
;; Iterator for VSHASIGMAD/VSHASIGMAW
(define_mode_iterator CR_hash [V4SI V2DI])
;; Iterator for the other crypto functions
(define_int_iterator CR_code [UNSPEC_VCIPHER
UNSPEC_VNCIPHER
UNSPEC_VCIPHERLAST
UNSPEC_VNCIPHERLAST])
(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher")
(UNSPEC_VNCIPHER "vncipher")
(UNSPEC_VCIPHERLAST "vcipherlast")
(UNSPEC_VNCIPHERLAST "vncipherlast")])
;; 2 operand crypto instructions
(define_insn "crypto_<CR_insn>"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:V2DI 2 "register_operand" "v")]
CR_code))]
"TARGET_CRYPTO"
"<CR_insn> %0,%1,%2"
[(set_attr "type" "crypto")])
(define_insn "crypto_vpmsum<CR_char>"
[(set (match_operand:CR_mode 0 "register_operand" "=v")
(unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
(match_operand:CR_mode 2 "register_operand" "v")]
UNSPEC_VPMSUM))]
"TARGET_P8_VECTOR"
"vpmsum<CR_char> %0,%1,%2"
[(set_attr "type" "crypto")])
;; 3 operand crypto instructions
(define_insn "crypto_vpermxor_<mode>"
[(set (match_operand:CR_mode 0 "register_operand" "=v")
(unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
(match_operand:CR_mode 2 "register_operand" "v")
(match_operand:CR_mode 3 "register_operand" "v")]
UNSPEC_VPERMXOR))]
"TARGET_P8_VECTOR"
"vpermxor %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
;; 1 operand crypto instruction
(define_insn "crypto_vsbox"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")]
UNSPEC_VSBOX))]
"TARGET_CRYPTO"
"vsbox %0,%1"
[(set_attr "type" "crypto")])
;; Hash crypto instructions
(define_insn "crypto_vshasigma<CR_char>"
[(set (match_operand:CR_hash 0 "register_operand" "=v")
(unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v")
(match_operand:SI 2 "const_0_to_1_operand" "n")
(match_operand:SI 3 "const_0_to_15_operand" "n")]
UNSPEC_VSHASIGMA))]
"TARGET_CRYPTO"
"vshasigma<CR_char> %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
gcc/config/powerpcspe/darwin.opt 0 → 100644
; Darwin options for PPC port.
;
; Copyright (C) 2005-2017 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Waltivec-long-deprecated
Driver Alias(mwarn-altivec-long)
faltivec
Driver
; -ffix-and-continue and -findirect-data are for compatibility for old
; compilers.
ffix-and-continue
Driver RejectNegative Alias(mfix-and-continue)
findirect-data
Driver RejectNegative Alias(mfix-and-continue)
m64
Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code.
m32
Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code.
gcc/config/powerpcspe/darwin64.h 0 → 100644
/* Target definitions for PowerPC running Darwin (Mac OS X).
Copyright (C) 2006-2017 Free Software Foundation, Inc.
Contributed by Apple Computer Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \
| MASK_MULTIPLE | MASK_PPC_GFXOPT)
#undef DARWIN_ARCH_SPEC
#define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}"
#undef DARWIN_SUBARCH_SPEC
#define DARWIN_SUBARCH_SPEC DARWIN_ARCH_SPEC
#undef DARWIN_CRT2_SPEC
#define DARWIN_CRT2_SPEC ""
gcc/config/powerpcspe/darwin7.h 0 → 100644
/* Target definitions for Darwin 7.x (Mac OS X) systems.
Copyright (C) 2004-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Machine dependent libraries. Include libmx when compiling for
Darwin 7.0 and above, but before libSystem, since the functions are
actually in libSystem but for 7.x compatibility we want them to be
looked for in libmx first. Include libmx by default because otherwise
libstdc++ isn't usable. */
#undef LIB_SPEC
#define LIB_SPEC "%{!static:\
%:version-compare(!< 10.3 mmacosx-version-min= -lmx)\
-lSystem}"
#undef DEF_MIN_OSX_VERSION
#define DEF_MIN_OSX_VERSION "10.3.9"
gcc/config/powerpcspe/darwin8.h 0 → 100644
/* Target definitions for Darwin 8.0 and above (Mac OS X) systems.
Copyright (C) 2004-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Machine dependent libraries. Include libmx when compiling on
Darwin 7.0 and above, but before libSystem, since the functions are
actually in libSystem but for 7.x compatibility we want them to be
looked for in libmx first---but only do this if 7.x compatibility
is a concern, which it's not in 64-bit mode. Include
libSystemStubs when compiling on (not necessarily for) 8.0 and
above and not 64-bit long double. */
#undef LIB_SPEC
#define LIB_SPEC "%{!static:\
%{!mlong-double-64:%{pg:-lSystemStubs_profile;:-lSystemStubs}} \
%{!m64:%:version-compare(>< 10.3 10.4 mmacosx-version-min= -lmx)} -lSystem}"
gcc/config/powerpcspe/default64.h 0 → 100644
/* Definitions of target machine for GNU compiler,
for 64 bit powerpc linux defaulting to -m64.
Copyright (C) 2003-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define RS6000_CPU(NAME, CPU, FLAGS)
#include "rs6000-cpus.def"
#undef RS6000_CPU
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN)
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
#endif
gcc/config/powerpcspe/e300c2c3.md 0 → 100644
;; Pipeline description for Motorola PowerPC e300c3 core.
;; Copyright (C) 2008-2017 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
;; We don't simulate general issue queue (GIC). If we have SU insn
;; and then SU1 insn, they can not be issued on the same cycle
;; (although SU1 insn and then SU insn can be issued) because the SU
;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
;; multipass insn scheduling will find the situation and issue the SU1
;; insn and then the SU insn.
(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
;; We could describe completion buffers slots in combination with the
;; retirement units and the order of completion but the result
;; automaton would behave in the same way because we can not describe
;; real latency time with taking in order completion into account.
;; Actually we could define the real latency time by querying reserved
;; automaton units but the current scheduler uses latency time before
;; issuing insns and making any reservations.
;;
;; So our description is aimed to achieve a insn schedule in which the
;; insns would not wait in the completion buffer.
(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
;; Branch unit:
(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
;; IU:
(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
;; IU: This used to describe non-pipelined division.
(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
;; SRU:
(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
;; Here we simplified LSU unit description not describing the stages.
(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
;; FPU:
(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
;; The following units are used to make automata deterministic
(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
;; Some useful abbreviations.
(define_reservation "ppce300c3_decode"
"ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
(define_reservation "ppce300c3_issue"
"ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
(define_reservation "ppce300c3_retire"
"ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
(define_reservation "ppce300c3_iu_stage0"
"ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
+ppce300c3_retire")
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
(and (ior (eq_attr "type" "integer,insert,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppce300c3_branch" 1
(and (eq_attr "type" "jmpreg,branch")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
;; Multiply is non-pipelined but can be executed in any IU
(define_insn_reservation "ppce300c3_multiply" 2
(and (eq_attr "type" "mul")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
ppce300c3_iu_stage0+ppce300c3_retire")
;; Divide. We use the average latency time here. We omit reserving a
;; retire unit because of the result automata will be huge.
(define_insn_reservation "ppce300c3_divide" 20
(and (eq_attr "type" "div")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
ppce300c3_mu_div*19")
;; CR logical
(define_insn_reservation "ppce300c3_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mfcr
(define_insn_reservation "ppce300c3_mfcr" 1
(and (eq_attr "type" "mfcr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mtcrf
(define_insn_reservation "ppce300c3_mtcrf" 1
(and (eq_attr "type" "mtcr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mtjmpr
(define_insn_reservation "ppce300c3_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Float point instructions
(define_insn_reservation "ppce300c3_fpcompare" 3
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
; Divides are not pipelined
(define_insn_reservation "ppce300c3_sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
(define_insn_reservation "ppce300c3_ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
;; Loads
(define_insn_reservation "ppce300c3_load" 2
(and (eq_attr "type" "load")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpload" 2
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
;; Stores.
(define_insn_reservation "ppce300c3_store" 2
(and (eq_attr "type" "store")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpstore" 2
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
gcc/config/powerpcspe/e500.h 0 → 100644
/* Enable E500 support.
Copyright (C) 2003-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_SPE_ABI
#undef TARGET_SPE
#undef TARGET_FPRS
#undef TARGET_E500_SINGLE
#undef TARGET_E500_DOUBLE
#undef CHECK_E500_OPTIONS
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_FPRS (rs6000_float_gprs == 0)
#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
#define CHECK_E500_OPTIONS \
do { \
if (TARGET_SPE || TARGET_SPE_ABI \
|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
{ \
if (TARGET_ALTIVEC) \
error ("AltiVec and SPE instructions cannot coexist"); \
if (TARGET_VSX) \
error ("VSX and SPE instructions cannot coexist"); \
if (TARGET_64BIT) \
error ("64-bit SPE not supported"); \
if (TARGET_HARD_FLOAT && TARGET_FPRS) \
error ("E500 and FPRs not supported"); \
} \
} while (0)
gcc/config/powerpcspe/e500mc.md 0 → 100644
;; Pipeline description for Motorola PowerPC e500mc core.
;; Copyright (C) 2008-2017 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e500mc 32-bit SU(2), LSU, FPU, BPU
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; FP is half clocked, timings of other instructions are as in the e500v2.
(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
;; SU.
(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
;; MU.
(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
;; Non-pipelined division.
(define_cpu_unit "e500mc_mu_div" "e500mc_long")
;; LSU.
(define_cpu_unit "e500mc_lsu" "e500mc_most")
;; FPU.
(define_cpu_unit "e500mc_fpu" "e500mc_most")
;; Branch unit.
(define_cpu_unit "e500mc_bu" "e500mc_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
;; Some useful abbreviations.
(define_reservation "e500mc_decode"
"e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
(define_reservation "e500mc_issue"
"e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
(define_reservation "e500mc_retire"
"e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
(define_reservation "e500mc_su_stage0"
"e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
(and (eq_attr "type" "integer,add,logical,insert,cmp,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Multiply.
(define_insn_reservation "e500mc_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc_divide" 14
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
e500mc_mu_div*13")
;; Branch.
(define_insn_reservation "e500mc_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_bu,e500mc_retire")
;; CR logical.
(define_insn_reservation "e500mc_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_bu,e500mc_retire")
;; Mfcr.
(define_insn_reservation "e500mc_mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtcrf.
(define_insn_reservation "e500mc_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtjmpr.
(define_insn_reservation "e500mc_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Brinc.
(define_insn_reservation "e500mc_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Loads.
(define_insn_reservation "e500mc_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
;; Stores.
(define_insn_reservation "e500mc_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
;; The following ignores the retire unit to avoid a large automata.
;; Simple FP.
(define_insn_reservation "e500mc_simple_float" 8
(and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
;; FP.
(define_insn_reservation "e500mc_float" 8
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
(define_insn_reservation "e500mc_fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
(define_insn_reservation "e500mc_dmul" 10
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
;; FP divides are not pipelined.
(define_insn_reservation "e500mc_sdiv" 36
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
(define_insn_reservation "e500mc_ddiv" 66
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
gcc/config/powerpcspe/e500mc64.md 0 → 100644
;; Pipeline description for Freescale PowerPC e500mc64 core.
;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e500mc64 64-bit SU(2), LSU, FPU, BPU
;; Max issue 3 insns/clock cycle (includes 1 branch)
(define_automaton "e500mc64_most,e500mc64_long,e500mc64_retire")
(define_cpu_unit "e500mc64_decode_0,e500mc64_decode_1" "e500mc64_most")
(define_cpu_unit "e500mc64_issue_0,e500mc64_issue_1" "e500mc64_most")
(define_cpu_unit "e500mc64_retire_0,e500mc64_retire_1" "e500mc64_retire")
;; SU.
(define_cpu_unit "e500mc64_su0_stage0,e500mc64_su1_stage0" "e500mc64_most")
;; MU.
(define_cpu_unit "e500mc64_mu_stage0,e500mc64_mu_stage1" "e500mc64_most")
(define_cpu_unit "e500mc64_mu_stage2,e500mc64_mu_stage3" "e500mc64_most")
;; Non-pipelined division.
(define_cpu_unit "e500mc64_mu_div" "e500mc64_long")
;; LSU.
(define_cpu_unit "e500mc64_lsu" "e500mc64_most")
;; FPU.
(define_cpu_unit "e500mc64_fpu" "e500mc64_most")
;; Branch unit.
(define_cpu_unit "e500mc64_bu" "e500mc64_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e500mc64_decode_0" "e500mc64_most")
(define_cpu_unit "present_e500mc64_issue_0" "e500mc64_most")
(define_cpu_unit "present_e500mc64_retire_0" "e500mc64_retire")
(define_cpu_unit "present_e500mc64_su0_stage0" "e500mc64_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_e500mc64_decode_0" "e500mc64_decode_0")
(presence_set "present_e500mc64_issue_0" "e500mc64_issue_0")
(presence_set "present_e500mc64_retire_0" "e500mc64_retire_0")
(presence_set "present_e500mc64_su0_stage0" "e500mc64_su0_stage0")
;; Some useful abbreviations.
(define_reservation "e500mc64_decode"
"e500mc64_decode_0|e500mc64_decode_1+present_e500mc64_decode_0")
(define_reservation "e500mc64_issue"
"e500mc64_issue_0|e500mc64_issue_1+present_e500mc64_issue_0")
(define_reservation "e500mc64_retire"
"e500mc64_retire_0|e500mc64_retire_1+present_e500mc64_retire_0")
(define_reservation "e500mc64_su_stage0"
"e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
(and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
(define_insn_reservation "e500mc64_delayed" 2
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
(define_insn_reservation "e500mc64_two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Multiply.
(define_insn_reservation "e500mc64_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc64_divide" 14
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
e500mc64_mu_div*13")
;; Branch.
(define_insn_reservation "e500mc64_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_bu,e500mc64_retire")
;; CR logical.
(define_insn_reservation "e500mc64_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_bu,e500mc64_retire")
;; Mfcr.
(define_insn_reservation "e500mc64_mfcr" 4
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0,e500mc64_su1_stage0*3+e500mc64_retire")
;; Mtcrf.
(define_insn_reservation "e500mc64_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0+e500mc64_retire")
;; Mtjmpr.
(define_insn_reservation "e500mc64_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Brinc.
(define_insn_reservation "e500mc64_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Loads.
(define_insn_reservation "e500mc64_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
;; Stores.
(define_insn_reservation "e500mc64_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
;; The following ignores the retire unit to avoid a large automata.
;; FP.
(define_insn_reservation "e500mc64_float" 7
(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu")
; "e500mc64_decode,e500mc64_issue+e500mc64_fpu,nothing*5,e500mc64_retire")
;; FP divides are not pipelined.
(define_insn_reservation "e500mc64_sdiv" 20
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*19")
(define_insn_reservation "e500mc64_ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34")
gcc/config/powerpcspe/e5500.md 0 → 100644
;; Pipeline description for Freescale PowerPC e5500 core.
;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
;; Max issue 3 insns/clock cycle (includes 1 branch)
(define_automaton "e5500_most,e5500_long")
(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
;; SFX.
(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
;; CFX.
(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
;; Non-pipelined division.
(define_cpu_unit "e5500_cfx_div" "e5500_long")
;; LSU.
(define_cpu_unit "e5500_lsu" "e5500_most")
;; FPU.
(define_cpu_unit "e5500_fpu" "e5500_long")
;; BU.
(define_cpu_unit "e5500_bu" "e5500_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e5500_decode_0" "e5500_most")
(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
(presence_set "present_e5500_decode_0" "e5500_decode_0")
(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
;; Some useful abbreviations.
(define_reservation "e5500_decode"
"e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
(define_reservation "e5500_sfx"
"e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
(and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_delayed" 2
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx*2")
(define_insn_reservation "e5500_two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
(define_insn_reservation "e5500_three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
;; SFX - Mfcr.
(define_insn_reservation "e5500_mfcr" 4
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx_0*4")
;; SFX - Mtcrf.
(define_insn_reservation "e5500_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx_0")
;; SFX - Mtjmpr.
(define_insn_reservation "e5500_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
;; CFX - Multiply.
(define_insn_reservation "e5500_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
(define_insn_reservation "e5500_multiply_i" 5
(and (eq_attr "type" "mul")
(ior (eq_attr "dot" "yes")
(eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,\
e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
;; CFX - Divide.
(define_insn_reservation "e5500_divide" 16
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*15")
(define_insn_reservation "e5500_divide_d" 26
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*25")
;; LSU - Loads.
(define_insn_reservation "e5500_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
;; LSU - Stores.
(define_insn_reservation "e5500_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
;; FP.
(define_insn_reservation "e5500_float" 7
(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu")
(define_insn_reservation "e5500_sdiv" 20
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu*20")
(define_insn_reservation "e5500_ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu*35")
;; BU.
(define_insn_reservation "e5500_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_bu")
;; BU - CR logical.
(define_insn_reservation "e5500_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_bu")
gcc/config/powerpcspe/powerpcspe-builtin.def 0 → 100644
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gcc/config/powerpcspe/powerpcspe-c.c 0 → 100644
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gcc/config/powerpcspe/powerpcspe.c 0 → 100644
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gcc/config/powerpcspe/powerpcspe.h 0 → 100644
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gcc/config/powerpcspe/powerpcspe.md 0 → 100644
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gcc/config/powerpcspe/spe.md 0 → 100644
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gcc/config/powerpcspe/vsx.md 0 → 100644
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