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riscv-gcc-1
Commit 83199882 by Richard Kenner
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Use proper modes and predicates for {sign,zero}_extract. 

From-SVN: r11511
parent d7cd794f
Showing with 234 additions and 163 deletions
gcc/config/fx80/fx80.md
;;- Machine description for GNU C compiler for Alliant FX systems
;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
;; Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
;; Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
;; and Joe Weening (weening@gang-of-four.stanford.edu).
......@@ -195,7 +195,7 @@
;; Recognizers for btst instructions.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
......@@ -203,7 +203,7 @@
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(match_operand:SI 1 "general_operand" "di"))))]
......@@ -215,7 +215,7 @@
;; are automatically masked to 3 or 5 bits.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(and:SI
......@@ -225,7 +225,7 @@
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(minus:SI (const_int 31)
(and:SI
......@@ -237,7 +237,7 @@
;; Nonoffsettable mem refs are ok in this one pattern
;; since we don't try to adjust them.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "general_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT
......@@ -250,7 +250,7 @@
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "general_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT"
......@@ -1656,7 +1656,7 @@
;; which can usually be done with move instructions.
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "general_operand" "d"))]
......@@ -1686,7 +1686,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&d")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
(zero_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
"TARGET_68020 && TARGET_BITFIELD
......@@ -1716,7 +1716,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
(sign_extract:SI (match_operand:SI 1 "register_operand" "do")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
"TARGET_68020 && TARGET_BITFIELD
......@@ -1744,26 +1744,42 @@
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
(define_insn "extv"
[(set (match_operand:SI 0 "general_operand" "=d,d")
(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
(match_operand:SI 2 "general_operand" "di,di")
(match_operand:SI 3 "general_operand" "di,di")))]
(define_expand "extv"
[(set (match_operand:SI 0 "general_operand" "")
(sign_extract:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts [%c3,%c2]%1,%0")
(define_insn "extzv"
[(set (match_operand:SI 0 "general_operand" "=d,d")
(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
(match_operand:SI 2 "general_operand" "di,di")
(match_operand:SI 3 "general_operand" "di,di")))]
(define_expand "extzv"
[(set (match_operand:SI 0 "general_operand" "")
(zero_extract:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfextu [%c3,%c2]%1,%0")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
(match_operand:SI 1 "general_operand" "di,di")
(match_operand:SI 2 "general_operand" "di,di"))
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
(match_operand:SI 3 "const_int_operand" "i,i")))]
"TARGET_68020 && TARGET_BITFIELD
......@@ -1777,9 +1793,9 @@
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
(match_operand:SI 1 "general_operand" "di,di")
(match_operand:SI 2 "general_operand" "di,di"))
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
"*
......@@ -1789,9 +1805,9 @@
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
(match_operand:SI 1 "general_operand" "di,di")
(match_operand:SI 2 "general_operand" "di,di"))
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
"*
......@@ -1800,11 +1816,19 @@
return \"bfset [%c2,%c1]%0\";
}")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
(match_operand:SI 1 "general_operand" "di,di")
(match_operand:SI 2 "general_operand" "di,di"))
(match_operand:SI 3 "general_operand" "d,d"))]
(define_expand "insv"
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" ""))
(match_operand:SI 3 "general_operand" ""))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 3 "general_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,[%c2,%c1]%0")
......@@ -1813,7 +1837,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
......@@ -1821,14 +1845,14 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "general_operand" "di")
(match_operand:SI 3 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfextu [%c3,%c2]%1,%0")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int 0))]
......@@ -1840,7 +1864,7 @@
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(const_int -1))]
......@@ -1852,7 +1876,7 @@
}")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "general_operand" "di")
(match_operand:SI 2 "general_operand" "di"))
(match_operand:SI 3 "general_operand" "d"))]
......@@ -1893,7 +1917,7 @@
;;; now handle the register cases
(define_insn ""
[(set (cc0)
(zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
(zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "general_operand" "di")))]
"TARGET_68020 && TARGET_BITFIELD"
......
gcc/config/gmicro/gmicro.md
;;- Machine description for GNU compiler, Fujitsu Gmicro Version
;; Copyright (C) 1990, 1994 Free Software Foundation, Inc.
;; Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
;; Contributed by M.Yuhara, Fujitsu Laboratories LTD.
;; This file is part of GNU CC.
......@@ -221,21 +221,14 @@
;; Recognizers for btst instructions.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "general_operand" "rmi")))]
""
"btst %1.w,%0.b")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "rmi")))]
""
"btst %1.w,%0.h")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "rmi")))]
""
......@@ -246,7 +239,7 @@
;; are automatically masked to 3 or 5 bits when the base is a register.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(and:SI
(match_operand:SI 1 "general_operand" "rmi")
......@@ -255,7 +248,7 @@
"btst %1.w,%0.b")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r")
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
(const_int 1)
(and:SI
(match_operand:SI 1 "general_operand" "rmi")
......@@ -268,7 +261,9 @@
(define_insn ""
[(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm")))
[(set (cc0) (and:SI (sign_extend:SI
(sign_extend:HI
(match_operand:QI 0 "nonimmediate_operand" "rm")))
(match_operand:SI 1 "general_operand" "i")))]
"(GET_CODE (operands[1]) == CONST_INT
&& (unsigned) INTVAL (operands[1]) < 0x100
......@@ -1990,7 +1985,7 @@
;; Should I add mode_dependent_address_p ????
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
(match_operand:SI 1 "immediate_operand" "i")
(match_operand:SI 2 "immediate_operand" "i"))
(match_operand:SI 3 "general_operand" "rm"))]
......@@ -2025,7 +2020,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&r")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
(zero_extract:SI (match_operand:SI 1 "register_operand" "rm")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD
......@@ -2096,7 +2091,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD
......@@ -2173,18 +2168,34 @@
;; r.w m r.w/# rmi
;; %0 %1 %2 %3
(define_insn "extv"
(define_expand "extv"
[(set (match_operand:SI 0 "general_operand" "")
(sign_extract:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
"TARGET_BITFIELD"
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:SI 2 "general_operand" "ri")
(match_operand:SI 3 "general_operand" "rmi")))]
"TARGET_BITFIELD"
"bfext %3,%2,%1,%0")
(define_insn "extzv"
(define_expand "extzv"
[(set (match_operand:SI 0 "general_operand" "")
(zero_extract:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
"TARGET_BITFIELD"
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:SI 2 "general_operand" "ri")
(match_operand:SI 3 "general_operand" "rmi")))]
"TARGET_BITFIELD"
......@@ -2198,13 +2209,22 @@
;; 0 1 2 3
(define_insn "insv"
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m")
(define_expand "insv"
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" ""))
(match_operand:SI 3 "general_operand" ""))]
"TARGET_BITFIELD"
"")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m,m")
(match_operand:SI 1 "general_operand" "r,i")
(match_operand:SI 2 "general_operand" "rmi,i"))
(match_operand:SI 3 "general_operand" "ri,ri"))]
"TARGET_BITFIELD"
"bfinsu %3,%2,%1,%0")
;;; bfins/bfinsu ????????
;; == == == == == == == == == == == == ==
......@@ -2225,7 +2245,7 @@
;;
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD"
......@@ -2242,7 +2262,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_BITFIELD"
......
gcc/config/i386/i386.md
;; GCC machine description for Intel X86.
;; Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc.
;; Copyright (C) 1988, 1994, 1995, 1996 Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; This file is part of GNU CC.
......@@ -1127,9 +1127,9 @@
}
/* If we are loading a floating point constant that isn't 0 or 1
into a register, indicate we need the pic register loaded. This could
be optimized into stores of constants if the target eventually moves
to memory, but better safe than sorry. */
into a register, indicate we need the pic register loaded. This could
be optimized into stores of constants if the target eventually moves
to memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
......@@ -1321,10 +1321,10 @@ to memory, but better safe than sorry. */
DONE;
}
/* If we are loading a floating point constant that isn't 0 or 1 into a register,
indicate we need the pic register loaded. This could be optimized into stores
of constants if the target eventually moves to memory, but better safe than
sorry. */
/* If we are loading a floating point constant that isn't 0 or 1 into a
register, indicate we need the pic register loaded. This could be
optimized into stores of constants if the target eventually moves to
memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
......@@ -1415,10 +1415,11 @@ to memory, but better safe than sorry. */
"* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);")
;; For the purposes of regclass, prefer FLOAT_REGS.
(define_insn "movdf_normal"
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
(match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM)"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
......@@ -1508,9 +1509,9 @@ to memory, but better safe than sorry. */
}
/* If we are loading a floating point constant that isn't 0 or 1
into a register, indicate we need the pic register loaded. This could
be optimized into stores of constants if the target eventually moves
to memory, but better safe than sorry. */
into a register, indicate we need the pic register loaded. This could
be optimized into stores of constants if the target eventually moves
to memory, but better safe than sorry. */
if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) != MEM
&& GET_CODE (operands[1]) == CONST_DOUBLE
......@@ -1598,10 +1599,11 @@ to memory, but better safe than sorry. */
""
"* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);")
(define_insn "movxf_normal"
(define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
(match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
"(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
|| (GET_CODE (operands[1]) != MEM)"
"*
{
int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
......@@ -4619,6 +4621,8 @@ to memory, but better safe than sorry. */
;; This usually looses. But try a define_expand to recognize a few case
;; we can do efficiently, such as accessing the "high" QImode registers,
;; %ah, %bh, %ch, %dh.
;; ??? Note this has a botch on the mode of operand 0, which needs to be
;; fixed if this is ever enabled.
(define_insn "insv"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r")
(match_operand:SI 1 "immediate_operand" "i")
......@@ -4673,23 +4677,6 @@ to memory, but better safe than sorry. */
FAIL;
}")
;; ??? Are these constraints right?
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo")
(const_int 8)
(const_int 8))
(match_operand:QI 1 "general_operand" "qn"))]
""
"*
{
if (REG_P (operands[0]))
return AS2 (mov%B0,%1,%h0);
operands[0] = adj_offsettable_operand (operands[0], 1);
return AS2 (mov%B0,%1,%0);
}")
*/
;; On i386, the register count for a bit operation is *not* truncated,
;; so SHIFT_COUNT_TRUNCATED must not be defined.
......@@ -4702,7 +4689,7 @@ to memory, but better safe than sorry. */
;; General bit set and clear.
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
(const_int 1)
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "const_int_operand" "n"))]
......@@ -4801,7 +4788,7 @@ to memory, but better safe than sorry. */
;; The CPU may access unspecified bytes around the actual target byte.
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n")))]
"GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
......
gcc/config/tahoe/tahoe.md
;; Machine description for GNU compiler, Tahoe version
;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
;; Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
;; This file is part of GNU CC.
......@@ -1946,7 +1946,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
......@@ -1958,7 +1958,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
......@@ -1970,7 +1970,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
......@@ -1982,7 +1982,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
(const_int 0))
......@@ -1996,7 +1996,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
......@@ -2008,7 +2008,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
......@@ -2020,7 +2020,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
......@@ -2032,7 +2032,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
(eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
(const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(const_int 0))
......
gcc/config/vax/vax.md
;;- Machine description for GNU compiler, Vax Version
;; Copyright (C) 1987, 1988, 1991, 1994, 1995 Free Software Foundation, Inc.
;; Copyright (C) 1987, 88, 91, 94, 95, 1996 Free Software Foundation, Inc.
;; This file is part of GNU CC.
......@@ -1322,7 +1322,7 @@
;; which can usually be done with move instructions.
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
(match_operand:QI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "general_operand" "g"))]
......@@ -1348,7 +1348,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=&g")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
......@@ -1373,7 +1373,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
......@@ -1401,7 +1401,7 @@
(define_insn ""
[(set (cc0)
(compare
(sign_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
(sign_extract:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g")))]
......@@ -1425,7 +1425,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
......@@ -1442,7 +1442,7 @@
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
......@@ -1469,7 +1469,7 @@
(define_insn ""
[(set (cc0)
(compare
(sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
(sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g")))]
......@@ -1488,7 +1488,7 @@
(define_insn "extv"
[(set (match_operand:SI 0 "general_operand" "=g")
(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
......@@ -1507,9 +1507,17 @@
return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
}")
(define_insn "extzv"
(define_expand "extzv"
[(set (match_operand:SI 0 "general_operand" "")
(zero_extract:SI (match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
""
"")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
(match_operand:QI 2 "general_operand" "g")
(match_operand:SI 3 "general_operand" "g")))]
""
......@@ -1529,8 +1537,16 @@
return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
}")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+g")
(define_expand "insv"
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" ""))
(match_operand:SI 3 "general_operand" ""))]
""
"")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g"))]
......@@ -1538,7 +1554,7 @@
"insv %3,%2,%1,%0")
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+r")
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g"))
(match_operand:SI 3 "general_operand" "g"))]
......@@ -1660,7 +1676,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
(ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))
......@@ -1674,7 +1690,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
(eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))
......
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