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riscv-gcc-1
Commit 82e86dc6 by Uros Bizjak
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i386.md: Remove empty predicates and/or constraints. 

	* config/i386/i386.md: Remove empty predicates and/or constraints.
	* config/i386/sync.md: Ditto.
	* config/i386/sse.md: Ditto.
	* config/i386/mmx.md: Ditto.
	* config/i386/pentium.md: Ditto.
	* config/i386/athlon.md: Ditto.

From-SVN: r185505
parent e5552514
Showing with 80 additions and 81 deletions
gcc/ChangeLog
2012-03-18 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md: Remove empty predicates and/or constraints.
* config/i386/sync.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/mmx.md: Ditto.
* config/i386/pentium.md: Ditto.
* config/i386/athlon.md: Ditto.
2012-03-16 Richard Guenther <rguenther@suse.de>
PR tree-optimization/52603
......@@ -38,7 +47,7 @@
(vect_is_simple_use): Treat all constants as vec_constant_def.
2012-03-16 Richard Guenther <rguenther@suse.de>
Kai Tietz <ktietz@redhat.com>
Kai Tietz <ktietz@redhat.com>
PR middle-end/48814
* gimplify.c (gimplify_self_mod_expr): Evaluate postfix
......@@ -131,8 +140,7 @@
2012-03-15 Jakub Jelinek <jakub@redhat.com>
PR target/52568
* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New
function.
* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New function.
(ix86_expand_vec_perm_const_1): Use it.
PR target/52568
......@@ -209,8 +217,8 @@
* config.gcc (target_type_format_char): New. Document it. Set it for
arm*-*-* .
* configure.ac (gnu_unique_option): Use target_type_format_char in test.
Comment rationale.
* configure.ac (gnu_unique_option): Use target_type_format_char
in test. Comment rationale.
* configure: Regenerate .
2012-03-15 Jakub Jelinek <jakub@redhat.com>
......@@ -363,8 +371,7 @@
* configure.ac (gcc_cv_ld_hidden): Remove *-*-solaris2.8*.
(ld_tls_support): Remove Solaris 8 references.
(lwp_dir, lwp_spec): Remove support for alternate thread library.
* acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.*
tests.
* acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.* tests.
* configure: Regenerate.
* config.in: Regenerate.
......@@ -435,8 +442,7 @@
2012-03-14 Martin Jambor <mjambor@suse.cz>
* expr.c (expand_assignment): Use expand_expr with EXPAND_WRITE
when expanding MEM_REFs, MEM_TARGET_REFs and handled_component
bases.
when expanding MEM_REFs, MEM_TARGET_REFs and handled_component bases.
(expand_expr_real_1): Do not handle misalignment if modifier is
EXPAND_WRITE.
......@@ -451,9 +457,8 @@
2012-03-14 Richard Guenther <rguenther@suse.de>
PR middle-end/52582
* gimple-fold.c (canonicalize_constructor_val): Make sure
we have a cgraph node for a FUNCTION_DECL that comes from
a constructor.
* gimple-fold.c (canonicalize_constructor_val): Make sure we have
a cgraph node for a FUNCTION_DECL that comes from a constructor.
(gimple_get_virt_method_for_binfo): Likewise.
2012-03-14 Richard Guenther <rguenther@suse.de>
......@@ -647,9 +652,8 @@
* config/i386/i386.c (ix86_option_override_internal): Properly
set ix86_gen_leave and ix86_gen_monitor. Check Pmode == DImode,
instead of TARGET_64BIT, to set ix86_gen_add3, ix86_gen_sub3,
ix86_gen_one_cmpl2, ix86_gen_andsp,
ix86_gen_allocate_stack_worker, ix86_gen_adjust_stack_and_probe
and ix86_gen_probe_stack_range.
ix86_gen_one_cmpl2, ix86_gen_andsp, ix86_gen_allocate_stack_worker,
ix86_gen_adjust_stack_and_probe and ix86_gen_probe_stack_range.
* config/i386/sse.md (sse3_monitor64): Renamed to ...
(sse3_monitor64_<mode>): This.
......@@ -691,9 +695,8 @@
(alpha*-dec-osf*): Remove.
* configure: Regenerate.
* config/alpha/host-osf.c, config/alpha/osf5.h,
config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf:
Remove.
* config/alpha/host-osf.c, config/alpha/osf5.h, config/alpha/osf5.opt,
config/alpha/va_list.h, config/alpha/x-osf: Remove.
* config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove.
* config/alpha/alpha.c (struct machine_function): Update comment.
......@@ -784,10 +787,9 @@
2012-03-12 Richard Guenther <rguenther@suse.de>
* tree-sra.c (create_access_replacement): Only rename the
replacement if we can rewrite it into SSA form. Properly
mark register typed replacements that we cannot rewrite
with TREE_ADDRESSABLE.
* tree-sra.c (create_access_replacement): Only rename the replacement
if we can rewrite it into SSA form. Properly mark register typed
replacements that we cannot rewrite with TREE_ADDRESSABLE.
* tree-cfg.c (verify_expr): Fix BIT_FIELD_REF verification
for aggregate or BLKmode results.
......@@ -802,8 +804,7 @@
2012-02-12 Kirill Yukhin <kirill.yukhin@intel.com>
* doc/invoke.texi: Document -mrtm option.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET):
New.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET): New.
(OPTION_MASK_ISA_RTM_UNSET): Ditto.
(ix86_handle_option): Handle OPT_mrtm.
* config.gcc (i[34567]86-*-*): Add rtmintrin.h and
......@@ -814,8 +815,8 @@
__RTM__ if needed.
(ix86_target_string): Define -mrtm option.
(PTA_RTM): New.
(ix86_option_override_internal): Extend "corei7-avx" with
RTM option. Handle new option.
(ix86_option_override_internal): Extend "corei7-avx" with RTM option.
Handle new option.
(ix86_valid_target_attribute_inner_p): Add OPT_mrtm.
(ix86_builtins): Add IX86_BUILTIN_XBEGIN, IX86_BUILTIN_XEND,
IX86_BUILTIN_XTEST.
......@@ -835,15 +836,14 @@
(xtest): Ditto.
(xtest_1): Ditto.
* config/i386/i386.opt (mrtm): New.
* config/i386/immintrin.h: Include rtmintrin.h and
xtestintrin.h.
* config/i386/immintrin.h: Include rtmintrin.h and xtestintrin.h.
* config/i386/rtmintrin.h: New header.
* config/i386/xtestintrin.h: Ditto.
2012-03-12 Tristan Gingold <gingold@adacore.com>
* ginclude/stddef.h: Adjust previous patch. Use __VMS__ instead
of VMS.
* ginclude/stddef.h: Adjust previous patch.
Use __VMS__ instead of VMS.
2012-03-12 Uros Bizjak <ubizjak@gmail.com>
......@@ -857,8 +857,7 @@
(C Dialect Options): Move -no-integrated-cpp documentation
from here...
(Preprocessor Options): ...to here. Rewrite the description
so it makes more sense, and remove discussion of merging
front ends.
so it makes more sense, and remove discussion of merging front ends.
2012-03-11 H.J. Lu <hongjiu.lu@intel.com>
......
gcc/config/i386/athlon.md
......@@ -40,7 +40,7 @@
(cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,leave")
(const_string "vector")
(and (eq_attr "type" "push")
(match_operand 1 "memory_operand" ""))
(match_operand 1 "memory_operand"))
(const_string "vector")
(and (eq_attr "type" "fmov")
(and (eq_attr "memory" "load,store")
......@@ -574,17 +574,17 @@
(define_insn_reservation "athlon_movlpd_load" 0
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-direct,athlon-fpload,athlon-fany")
(define_insn_reservation "athlon_movlpd_load_k8" 2
(and (eq_attr "cpu" "k8")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-direct,athlon-fploadk8,athlon-fstore")
(define_insn_reservation "athlon_movsd_load_generic64" 2
(and (eq_attr "cpu" "generic64")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand" "")))
(match_operand:DF 1 "memory_operand")))
"athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)")
(define_insn_reservation "athlon_movaps_load_k8" 2
(and (eq_attr "cpu" "k8,generic64")
......
gcc/config/i386/i386.md
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/i386/pentium.md
......@@ -47,22 +47,22 @@
(eq_attr "type" "ibr")
(const_string "pv")
(and (eq_attr "type" "ishift")
(match_operand 2 "const_int_operand" ""))
(match_operand 2 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate")
(match_operand 2 "const1_operand" ""))
(match_operand 2 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "ishift1")
(match_operand 1 "const_int_operand" ""))
(match_operand 1 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate1")
(match_operand 1 "const1_operand" ""))
(match_operand 1 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand" ""))
(match_operand 0 "constant_call_address_operand"))
(const_string "pv")
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand" ""))
(match_operand 1 "constant_call_address_operand"))
(const_string "pv")
]
(const_string "np")))
......@@ -167,7 +167,7 @@
(define_insn_reservation "pent_fpstore" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "fmov")
(ior (match_operand 1 "immediate_operand" "")
(ior (match_operand 1 "immediate_operand")
(eq_attr "memory" "store"))))
"(pentium-fp+pentium-np)*2")
......
gcc/config/i386/sync.md
......@@ -46,7 +46,7 @@
})
(define_insn "*sse2_lfence"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
"TARGET_SSE2"
"lfence"
......@@ -65,7 +65,7 @@
})
(define_insn "*sse_sfence"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
"TARGET_SSE || TARGET_3DNOW_A"
"sfence"
......@@ -84,7 +84,7 @@
})
(define_insn "mfence_sse2"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"TARGET_64BIT || TARGET_SSE2"
"mfence"
......@@ -94,7 +94,7 @@
(set_attr "memory" "unknown")])
(define_insn "mfence_nosse"
[(set (match_operand:BLK 0 "" "")
[(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
(clobber (reg:CC FLAGS_REG))]
"!(TARGET_64BIT || TARGET_SSE2)"
......@@ -102,7 +102,7 @@
[(set_attr "memory" "unknown")])
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")] ;; model
[(match_operand:SI 0 "const_int_operand")] ;; model
""
{
/* Unless this is a SEQ_CST fence, the i386 memory model is strong
......@@ -142,9 +142,9 @@
])
(define_expand "atomic_load<mode>"
[(set (match_operand:ATOMIC 0 "register_operand" "")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
[(set (match_operand:ATOMIC 0 "register_operand")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand")
(match_operand:SI 2 "const_int_operand")]
UNSPEC_MOVA))]
""
{
......@@ -200,9 +200,9 @@
})
(define_expand "atomic_store<mode>"
[(set (match_operand:ATOMIC 0 "memory_operand" "")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
[(set (match_operand:ATOMIC 0 "memory_operand")
(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand")
(match_operand:SI 2 "const_int_operand")]
UNSPEC_MOVA))]
""
{
......@@ -305,14 +305,14 @@
(set_attr "mode" "DI")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:QI 0 "register_operand" "") ;; bool success output
(match_operand:SWI124 1 "register_operand" "") ;; oldval output
(match_operand:SWI124 2 "memory_operand" "") ;; memory
(match_operand:SWI124 3 "register_operand" "") ;; expected input
(match_operand:SWI124 4 "register_operand" "") ;; newval input
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; success model
(match_operand:SI 7 "const_int_operand" "")] ;; failure model
[(match_operand:QI 0 "register_operand") ;; bool success output
(match_operand:SWI124 1 "register_operand") ;; oldval output
(match_operand:SWI124 2 "memory_operand") ;; memory
(match_operand:SWI124 3 "register_operand") ;; expected input
(match_operand:SWI124 4 "register_operand") ;; newval input
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; success model
(match_operand:SI 7 "const_int_operand")] ;; failure model
"TARGET_CMPXCHG"
{
emit_insn (gen_atomic_compare_and_swap_single<mode>
......@@ -332,14 +332,14 @@
(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:QI 0 "register_operand" "") ;; bool success output
(match_operand:CASMODE 1 "register_operand" "") ;; oldval output
(match_operand:CASMODE 2 "memory_operand" "") ;; memory
(match_operand:CASMODE 3 "register_operand" "") ;; expected input
(match_operand:CASMODE 4 "register_operand" "") ;; newval input
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; success model
(match_operand:SI 7 "const_int_operand" "")] ;; failure model
[(match_operand:QI 0 "register_operand") ;; bool success output
(match_operand:CASMODE 1 "register_operand") ;; oldval output
(match_operand:CASMODE 2 "memory_operand") ;; memory
(match_operand:CASMODE 3 "register_operand") ;; expected input
(match_operand:CASMODE 4 "register_operand") ;; newval input
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; success model
(match_operand:SI 7 "const_int_operand")] ;; failure model
"TARGET_CMPXCHG"
{
if (<MODE>mode == DImode && TARGET_64BIT)
......@@ -448,7 +448,7 @@
[(set (match_operand:SWI 0 "register_operand" "=<r>")
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "+m")
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPECV_XCHG))
(set (match_dup 1)
(plus:SWI (match_dup 1)
......@@ -461,12 +461,12 @@
;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec}
;; followed by testing of flags instead of lock xadd and comparisons.
(define_peephole2
[(set (match_operand:SWI 0 "register_operand" "")
(match_operand:SWI 2 "const_int_operand" ""))
[(set (match_operand:SWI 0 "register_operand")
(match_operand:SWI 2 "const_int_operand"))
(parallel [(set (match_dup 0)
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "")
(match_operand:SI 4 "const_int_operand" "")]
[(match_operand:SWI 1 "memory_operand")
(match_operand:SI 4 "const_int_operand")]
UNSPECV_XCHG))
(set (match_dup 1)
(plus:SWI (match_dup 1)
......@@ -474,7 +474,7 @@
(clobber (reg:CC FLAGS_REG))])
(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_dup 0)
(match_operand:SWI 3 "const_int_operand" "")))]
(match_operand:SWI 3 "const_int_operand")))]
"peep2_reg_dead_p (3, operands[0])
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2])
== -(unsigned HOST_WIDE_INT) INTVAL (operands[3])
......@@ -492,7 +492,7 @@
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (unspec_volatile:SWI
[(match_operand:SWI 0 "memory_operand" "+m")
(match_operand:SI 3 "const_int_operand" "")]
(match_operand:SI 3 "const_int_operand")]
UNSPECV_XCHG)
(match_operand:SWI 2 "const_int_operand" "i")))
(set (match_dup 0)
......@@ -521,7 +521,7 @@
[(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output
(unspec_volatile:SWI
[(match_operand:SWI 1 "memory_operand" "+m") ;; memory
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPECV_XCHG))
(set (match_dup 1)
(match_operand:SWI 2 "register_operand" "0"))] ;; input
......@@ -533,7 +533,7 @@
(unspec_volatile:SWI
[(plus:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
......@@ -557,7 +557,7 @@
(unspec_volatile:SWI
[(minus:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
......@@ -581,7 +581,7 @@
(unspec_volatile:SWI
[(any_logic:SWI (match_dup 0)
(match_operand:SWI 1 "nonmemory_operand" "<r><i>"))
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
......
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