Support for official Sparc V9 ABI:

        * sparc.c (sparc_override_options): Force stack bias off for !arch64.
        Care for flag_pcc_struct_return default.
        (output_move_quad): Rewrite to move by halves on v9 and in the
        proper direction.
        (move_quad_direction): New function.
        (output_fp_move_quad): Use it to determine the direction of copy.
        (function_arg_slotno): Return -1 for FP reg overflow as well.
        (function_arg_record_value*): New functions.
        (function_arg): Use them.  Streamline unprototyped parameter passing.
        (function_arg_pass_by_reference): Pass TCmode by reference.
        (function_value): New function.
        * sparc.h (PTRDIFF_TYPE, SIZE_TYPE): For -pedantic's sake, don't use
        long long in 64-bit mode.
        (RETURN_IN_MEMORY): v9 returns structs < 32-bytes in regs.
        (DEFAULT_PCC_STRUCT_RETURN): Make the default detectable.
        (BASE_RETURN_VALUE_REG): Consider complex float types for arch64.
        (BASE_OUTGOING_VALUE_REG, BASE_PASSING_ARG_REG): Likewise.
        (BASE_INCOMING_ARG_REG): Likewise.
        (FUNCTION_VALUE): Call function_value.
        (FUNCTION_OUTGOING_VALUE, LIBCALL_VALUE): Likewise.
        * sparc.md (movdi_sp32_v9): Disable for arch64.
        (movsf, movdf, movtf): Sort all ulternatives using fp regs first.
        (call_value_address_sp64): Remove register class constraints.
        (call_value_symbolic_sp64): Likewise.
        (nonlocal_goto): Pass label reg directly to goto_handlers.  Constrain
        v9 case to 32-bit constants.
        (goto_handler_and_restore_v9): Provide a version for arch64.
        * sparc/linux64.h (SIZE_TYPE, PTRDIFF_TYPE): Remove private definition.
        * sparc/sp64-aout.h (TARGET_DEFAULT): Turn on stack bias.
        (CPP_PREDEFINES): New.
        * sparc/sp64-elf.h: Likewise.
        (PREFERRED_DEBUGGING_TYPE): Dwarf2.
        (ASM_OUTPUT_DWARF2_ADDR_CONST): New.
        * sparc/sysv4.h (SIZE_TYPE, PTRDIFF_TYPE): Undo svr4.h's changes.

From-SVN: r19526

gcc/ChangeLog

+Sun May  3 13:51:34 PDT 1998  Richard Henerson  <rth@cygnus.com>
+
+	Support for official Sparc V9 ABI:
+	* sparc.c (sparc_override_options): Force stack bias off for !arch64.
+	Care for flag_pcc_struct_return default.
+	(output_move_quad): Rewrite to move by halves on v9 and in the
+	proper direction.
+	(move_quad_direction): New function.
+	(output_fp_move_quad): Use it to determine the direction of copy.
+	(function_arg_slotno): Return -1 for FP reg overflow as well.
+	(function_arg_record_value*): New functions.
+	(function_arg): Use them.  Streamline unprototyped parameter passing.
+	(function_arg_pass_by_reference): Pass TCmode by reference.
+	(function_value): New function.
+	* sparc.h (PTRDIFF_TYPE, SIZE_TYPE): For -pedantic's sake, don't use
+	long long in 64-bit mode.
+	(RETURN_IN_MEMORY): v9 returns structs < 32-bytes in regs.
+	(DEFAULT_PCC_STRUCT_RETURN): Make the default detectable.
+	(BASE_RETURN_VALUE_REG): Consider complex float types for arch64.
+	(BASE_OUTGOING_VALUE_REG, BASE_PASSING_ARG_REG): Likewise.
+	(BASE_INCOMING_ARG_REG): Likewise.
+	(FUNCTION_VALUE): Call function_value.
+	(FUNCTION_OUTGOING_VALUE, LIBCALL_VALUE): Likewise.
+	* sparc.md (movdi_sp32_v9): Disable for arch64.
+	(movsf, movdf, movtf): Sort all ulternatives using fp regs first.
+	(call_value_address_sp64): Remove register class constraints.
+	(call_value_symbolic_sp64): Likewise.
+	(nonlocal_goto): Pass label reg directly to goto_handlers.  Constrain
+	v9 case to 32-bit constants.
+	(goto_handler_and_restore_v9): Provide a version for arch64.
+	* sparc/linux64.h (SIZE_TYPE, PTRDIFF_TYPE): Remove private definition.
+	* sparc/sp64-aout.h (TARGET_DEFAULT): Turn on stack bias.
+	(CPP_PREDEFINES): New.
+	* sparc/sp64-elf.h: Likewise.
+	(PREFERRED_DEBUGGING_TYPE): Dwarf2.
+	(ASM_OUTPUT_DWARF2_ADDR_CONST): New.
+	* sparc/sysv4.h (SIZE_TYPE, PTRDIFF_TYPE): Undo svr4.h's changes.
+
 Sat May 2 17:47:17 PDT 1998 Jeff Law  (law@cygnus.com)
 
 	* version.c: Bump for snapshot.

gcc/config/sparc/linux64.h

@@ -84,12 +84,6 @@ Boston, MA 02111-1307, USA.  */
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_MEDANY
 
-#undef SIZE_TYPE
-#define SIZE_TYPE "long long unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long long int"
-  
 #undef WCHAR_TYPE
 #define WCHAR_TYPE "long int"
    

gcc/config/sparc/sp64-aout.h

 /* Definitions of target machine for GNU compiler, for SPARC64, a.out.
-   Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1996, 1997, 1998  Free Software Foundation, Inc.
    Contributed by Doug Evans, dje@cygnus.com.
 
 This file is part of GNU CC.
@@ -28,8 +28,11 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
   (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
-   + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
+   + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
 
 /* The only code model supported is Medium/Low.  */
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_MEDLOW
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)"

gcc/config/sparc/sp64-elf.h

 /* Definitions of target machine for GNU compiler, for SPARC64, ELF.
-   Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1995, 1996, 1997, 1998  Free Software Foundation, Inc.
    Contributed by Doug Evans, dje@cygnus.com.
 
 This file is part of GNU CC.
@@ -29,19 +29,19 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (sparc64-elf)")
 
-/* A 64 bit v9 compiler without stack-bias,
-   in a Medium/Anywhere code model environment.
-   There is no stack bias as this configuration is intended for
-   embedded systems.  */
+/* A 64 bit v9 compiler in a Medium/Anywhere code model environment.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
 (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
- + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
+ + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
 
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
 
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dsparc -D__ELF__ -Acpu(sparc) -Amachine(sparc)"
+
 /* __svr4__ is used by the C library (FIXME) */
 #undef CPP_SUBTARGET_SPEC
 #define CPP_SUBTARGET_SPEC "-D__svr4__"
@@ -99,11 +99,6 @@ crtbegin.o%s \
 #undef LONG_DOUBLE_TYPE_SIZE
 #define LONG_DOUBLE_TYPE_SIZE 128
 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long long int"
-#undef SIZE_TYPE
-#define SIZE_TYPE "long long unsigned int"
-
 /* The medium/anywhere code model practically requires us to put jump tables
    in the text section as gcc is unable to distinguish LABEL_REF's of jump
    tables from other label refs (when we need to).  */
@@ -120,7 +115,7 @@ crtbegin.o%s \
 #define DBX_DEBUGGING_INFO
 
 #undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 
 /* Stabs doesn't use this, and it confuses a simulator.  */
 /* ??? Need to see what DWARF needs, if anything.  */
@@ -150,6 +145,9 @@ do {								\
   fputc ('\n', (FILE));						\
 } while (0)
 
+#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE, ADDR) \
+  fprintf ((FILE), "\t%s\t%s", UNALIGNED_LONGLONG_ASM_OP, (ADDR))
+
 /* ??? Not sure if this should be 4 or 8 bytes.  4 works for now.  */
 #define ASM_OUTPUT_DWARF_REF(FILE, LABEL) \
 do {								\

gcc/config/sparc/sparc.h

@@ -276,8 +276,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
 #define NO_BUILTIN_PTRDIFF_TYPE
 #define NO_BUILTIN_SIZE_TYPE
 #endif
-#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long long int" : "int")
-#define SIZE_TYPE (TARGET_ARCH64 ? "long long unsigned int" : "unsigned int")
+#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
+#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
 
 /* ??? This should be 32 bits for v9 but what can we do?  */
 #define WCHAR_TYPE "short unsigned int"
@@ -1078,18 +1078,24 @@ extern int sparc_mode_class[];
 #define INITIALIZE_PIC initialize_pic ()
 #define FINALIZE_PIC finalize_pic ()
 
+/* Pick a default value we can notice from override_options:
+   !v9: Default is on.
+   v9: Default is off.  */
+
+#define DEFAULT_PCC_STRUCT_RETURN -1
+
 /* Sparc ABI says that quad-precision floats and all structures are returned
    in memory.
    For v9: unions <= 32 bytes in size are returned in int regs,
-   structures up to 32 bytes are returned in int and fp regs.
-   FIXME: wip */
+   structures up to 32 bytes are returned in int and fp regs.  */
 
 #define RETURN_IN_MEMORY(TYPE)				\
 (TARGET_ARCH32						\
  ? (TYPE_MODE (TYPE) == BLKmode				\
     || TYPE_MODE (TYPE) == TFmode			\
     || TYPE_MODE (TYPE) == TCmode)			\
- : TYPE_MODE (TYPE) == BLKmode)
+ : (TYPE_MODE (TYPE) == BLKmode				\
+    && int_size_in_bytes (TYPE) > 32))
 
 /* Functions which return large structures get the address
    to place the wanted value at offset 64 from the frame.
@@ -1449,9 +1455,14 @@ extern char leaf_reg_remap[];
    : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
 
 /* When a parameter is passed in a register, stack space is still
-   allocated for it.  */
-/* This only takes into account the int regs.
-   fp regs are handled elsewhere.  */
+   allocated for it.
+   !v9: All 6 possible integer registers have backing store allocated.
+   v9: Only space for the arguments passed is allocated. */
+/* ??? Ideally, we'd use zero here (as the minimum), but zero has special
+   meaning to the backend.  Further, we need to be able to detect if a
+   varargs/unprototyped function is called, as they may want to spill more
+   registers than we've provided space.  Ugly, ugly.  So for now we retain
+   all 6 slots even for v9.  */
 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
 
 /* Keep the stack pointer constant throughout the function.
@@ -1472,24 +1483,28 @@ extern char leaf_reg_remap[];
 /* Some subroutine macros specific to this machine.
    When !TARGET_FPU, put float return values in the general registers,
    since we don't have any fp registers.  */
-#define BASE_RETURN_VALUE_REG(MODE) \
-  (TARGET_ARCH64 \
-   ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
+#define BASE_RETURN_VALUE_REG(MODE)					\
+  (TARGET_ARCH64							\
+   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)			\
    : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
-#define BASE_OUTGOING_VALUE_REG(MODE) \
-  (TARGET_ARCH64 \
-   ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
-      : TARGET_FLAT ? 8 : 24) \
+
+#define BASE_OUTGOING_VALUE_REG(MODE)				\
+  (TARGET_ARCH64						\
+   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32			\
+      : TARGET_FLAT ? 8 : 24)					\
    : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32	\
       : (TARGET_FLAT ? 8 : 24)))
-#define BASE_PASSING_ARG_REG(MODE) \
-  (TARGET_ARCH64 \
-   ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
+
+#define BASE_PASSING_ARG_REG(MODE)				\
+  (TARGET_ARCH64						\
+   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)		\
    : 8)
-#define BASE_INCOMING_ARG_REG(MODE) \
-  (TARGET_ARCH64 \
-   ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
-      : TARGET_FLAT ? 8 : 24) \
+
+/* ??? FIXME -- seems wrong for v9 structure passing... */
+#define BASE_INCOMING_ARG_REG(MODE)				\
+  (TARGET_ARCH64						\
+   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32			\
+      : TARGET_FLAT ? 8 : 24)					\
    : (TARGET_FLAT ? 8 : 24))
 
 /* Define this macro if the target machine has "register windows".  This
@@ -1515,19 +1530,20 @@ extern char leaf_reg_remap[];
 
 /* On SPARC the value is found in the first "output" register.  */
 
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
+extern struct rtx_def *function_value ();
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+  function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
 
 /* But the called function leaves it in the first "input" register.  */
 
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)  \
-  gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
+#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
+  function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
 
 /* Define how to find the value returned by a library function
    assuming the value has mode MODE.  */
 
-#define LIBCALL_VALUE(MODE)	\
-  gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG (MODE))
+#define LIBCALL_VALUE(MODE) \
+  function_value (NULL_TREE, (MODE), 1)
 
 /* 1 if N is a possible register number for a function value
    as seen by the caller.

gcc/config/sparc/sparc.md

@@ -2202,7 +2202,7 @@
 (define_insn "*movdi_sp32_v9"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,T,Q,r,r,?e,?e,?Q,?b")
 	(match_operand:DI 1 "general_operand" "r,J,r,Q,i,e,Q,e,J"))]
-  "TARGET_V9
+  "TARGET_V9 && ! TARGET_ARCH64
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode)
        || operands[1] == const0_rtx)
@@ -2297,7 +2297,7 @@
     case 3:
       return \"stx %r1,%0\";
     case 4:
-      return \"mov %1,%0\";
+      return \"fmovd %1,%0\";
     case 5:
       return \"ldd %1,%0\";
     case 6:
@@ -2367,8 +2367,8 @@
 ;; to be reloaded by putting the constant into memory.
 ;; It must come before the more general movsf pattern.
 (define_insn "*movsf_const_insn"
-  [(set (match_operand:SF 0 "general_operand" "=?r,f,m,d")
-	(match_operand:SF 1 "" "?F,m,G,G"))]
+  [(set (match_operand:SF 0 "general_operand" "=f,d,m,?r")
+	(match_operand:SF 1 "" "m,G,G,?F"))]
   "TARGET_FPU
    && GET_CODE (operands[1]) == CONST_DOUBLE
    && (GET_CODE (operands[0]) == REG
@@ -2378,19 +2378,19 @@
   switch (which_alternative)
     {
     case 0:
-      return singlemove_string (operands);
-    case 1:
       return \"ld %1,%0\";
+    case 1:
+      return \"fzeros %0\";
     case 2:
       return \"st %%g0,%0\";
     case 3:
-      return \"fzeros %0\";
+      return singlemove_string (operands);
     default:
       abort ();
     }
 }"
-  [(set_attr "type" "load,fpload,store,fpmove")
-   (set_attr "length" "2,1,1,1")])
+  [(set_attr "type" "fpload,fpmove,store,load")
+   (set_attr "length" "1,1,1,2")])
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
@@ -2403,19 +2403,19 @@
 }")
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=f,r,f,r,Q,Q")
-	(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "f,r,Q,Q,f,r"))]
+  [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=f,f,Q,r,r,Q")
+	(match_operand:SF 1 "reg_or_nonsymb_mem_operand"  "f,Q,f,r,Q,r"))]
   "TARGET_FPU
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode))"
   "@
    fmovs %1,%0
-   mov %1,%0
-   ld %1,%0
    ld %1,%0
    st %1,%0
+   mov %1,%0
+   ld %1,%0
    st %1,%0"
-  [(set_attr "type" "fpmove,move,fpload,load,fpstore,store")])
+  [(set_attr "type" "fpmove,fpload,fpstore,move,load,store")])
 
 ;; Exactly the same as above, except that all `f' cases are deleted.
 ;; This is necessary to prevent reload from ever trying to use a `f' reg
@@ -2492,8 +2492,8 @@
 }")
 
 (define_insn "*movdf_insn"
-  [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,e,r,Q,Q,e,r")
-	(match_operand:DF 1 "reg_or_nonsymb_mem_operand" "U,T,e,r,e,r,Q,Q"))]
+  [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=e,Q,e,T,U,r,Q,r")
+	(match_operand:DF 1 "reg_or_nonsymb_mem_operand"  "e,e,Q,U,T,r,r,Q"))]
   "TARGET_FPU
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"
@@ -2512,7 +2512,7 @@
 
 (define_insn "*movdf_no_e_insn"
   [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,r,Q,&r")
-	(match_operand:DF 1 "reg_or_nonsymb_mem_operand" "U,T,r,r,Q"))]
+	(match_operand:DF 1 "reg_or_nonsymb_mem_operand"  "U,T,r,r,Q"))]
   "! TARGET_FPU
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"
@@ -2619,8 +2619,8 @@
 }")
 
 (define_insn "*movtf_insn"
-  [(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=e,r,Q,Q,e,&r")
-	(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "e,r,e,r,Q,Q"))]
+  [(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=e,Q,e,r,Q,r")
+	(match_operand:TF 1 "reg_or_nonsymb_mem_operand"  "e,e,Q,r,r,Q"))]
   "TARGET_FPU
    && (register_operand (operands[0], TFmode)
        || register_operand (operands[1], TFmode))"
@@ -5517,7 +5517,8 @@ if (! TARGET_ARCH64)
   ""
   "*
 {
-  /* Some implementations are reported to have problems with
+  /* Some implementations (e.g. TurboSparc) are reported to have problems
+     with
 	foo: b,a foo
      i.e. an empty loop with the annul bit set.  The workaround is to use 
         foo: b foo; nop
@@ -5824,7 +5825,7 @@ if (! TARGET_ARCH64)
   [(set_attr "type" "call")])
 
 (define_insn "*call_value_address_sp64"
-  [(set (match_operand 0 "" "=rf")
+  [(set (match_operand 0 "" "")
 	(call (mem:SI (match_operand:DI 1 "address_operand" "p"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 15))]
@@ -5834,7 +5835,7 @@ if (! TARGET_ARCH64)
   [(set_attr "type" "call")])
 
 (define_insn "*call_value_symbolic_sp64"
-  [(set (match_operand 0 "" "=rf")
+  [(set (match_operand 0 "" "")
 	(call (mem:SI (match_operand:DI 1 "symbolic_operand" "s"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 15))]
@@ -5982,6 +5983,7 @@ if (! TARGET_ARCH64)
   rtx fp = operands[1];
   rtx stack = operands[2];
   rtx lab = operands[3];
+  rtx labreg;
 
   /* Trap instruction to flush all the register windows.  */
   emit_insn (gen_flush_register_windows ());
@@ -5995,7 +5997,8 @@ if (! TARGET_ARCH64)
 
   /* Find the containing function's current nonlocal goto handler,
      which will do any cleanups and then jump to the label.  */
-  emit_move_insn (gen_rtx (REG, Pmode, 8), lab);
+  labreg = gen_rtx (REG, Pmode, 8);
+  emit_move_insn (labreg, lab);
 
   /* Restore %fp from stack pointer value for containing function.
      The restore insn that follows will move this to %sp,
@@ -6007,16 +6010,18 @@ if (! TARGET_ARCH64)
   /*emit_insn (gen_rtx (USE, VOIDmode, frame_pointer_rtx));*/
   emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
   /* Return, restoring reg window and jumping to goto handler.  */
-  if (TARGET_V9 && GET_CODE (chain) == CONST_INT)
+  if (TARGET_V9 && GET_CODE (chain) == CONST_INT
+      && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff))
     {
-      emit_insn (gen_goto_handler_and_restore_v9 (static_chain_rtx, chain));
+      emit_insn (gen_goto_handler_and_restore_v9 (labreg, static_chain_rtx,
+						  chain));
       emit_barrier ();
       DONE;
     }
   /* Put in the static chain register the nonlocal label address.  */
   emit_move_insn (static_chain_rtx, chain);
   emit_insn (gen_rtx (USE, VOIDmode, static_chain_rtx));
-  emit_insn (gen_goto_handler_and_restore ());
+  emit_insn (gen_goto_handler_and_restore (labreg));
   emit_barrier ();
   DONE;
 }")
@@ -6029,20 +6034,31 @@ if (! TARGET_ARCH64)
   [(set_attr "type" "misc")])
 
 (define_insn "goto_handler_and_restore"
-  [(unspec_volatile [(reg:SI 8)] 2)]
-  "! TARGET_V9"
-  "jmp %%o0+0\;restore"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r")] 2)]
+  ""
+  "jmp %0+0\;restore"
   [(set_attr "type" "misc")
    (set_attr "length" "2")])
 
 (define_insn "goto_handler_and_restore_v9"
-  [(unspec_volatile [(reg:SI 8)
-		     (match_operand:SI 0 "register_operand" "=r,r")
-		     (match_operand:SI 1 "const_int_operand" "I,n")] 3)]
-  "TARGET_V9"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
+		     (match_operand:SI 1 "register_operand" "=r,r")
+		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+  "TARGET_V9 && ! TARGET_ARCH64"
+  "@
+   return %0+0\;mov %2,%Y1
+   sethi %%hi(%2),%1\;return %0+0\;or %Y1,%%lo(%2),%Y1"
+  [(set_attr "type" "misc")
+   (set_attr "length" "2,3")])
+
+(define_insn "*goto_handler_and_restore_v9_sp64"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
+		     (match_operand:DI 1 "register_operand" "=r,r")
+		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
+  "TARGET_V9 && TARGET_ARCH64"
   "@
-   return %%o0+0\;mov %1,%Y0
-   sethi %%hi(%1),%0\;return %%o0+0\;or %Y0,%%lo(%1),%Y0"
+   return %0+0\;mov %2,%Y1
+   sethi %%hi(%2),%1\;return %0+0\;or %Y1,%%lo(%2),%Y1"
   [(set_attr "type" "misc")
    (set_attr "length" "2,3")])
 

gcc/config/sparc/sysv4.h

@@ -33,6 +33,16 @@ Boston, MA 02111-1307, USA.  */
 
 #include "svr4.h"
 
+/* ??? Put back the SIZE_TYPE/PTRDIFF_TYPE definitions set by sparc.h.
+   Why, exactly, is svr4.h messing with this?  Seems like the chip 
+   would know best.  */
+
+#undef SIZE_TYPE
+#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
+
 /* Undefined some symbols which are defined in "svr4.h" but which are
    appropriate only for typical svr4 systems, but not for the specific
    case of svr4 running on a Sparc.  */