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lvzhengyang
riscv-gcc-1
Commits
82b06589
Commit
82b06589
authored
Mar 01, 2012
by
Joern Rennecke
Committed by
Joern Rennecke
Mar 01, 2012
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* config/epiphany/epiphany.md (movmisalign<mode>): New patterns.
From-SVN: r184766
parent
08b03910
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gcc/config/epiphany/epiphany.md
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gcc/ChangeLog
View file @
82b06589
2012-03-01 Joern Rennecke <joern.rennecke@embecosm.com>
* config/epiphany/epiphany.md (movmisalign<mode>): New patterns.
2012-03-01 Jeremy Bennett <jeremy.bennett@embecosm.com>
Joern Rennecke <joern.rennecke@embecosm.com>
...
...
gcc/config/epiphany/epiphany.md
View file @
82b06589
;; Machine description of the Adaptiva epiphany cpu for GNU C compiler
;; Copyright (C) 1994, 1997, 1998, 1999, 2000, 2004, 2005, 2007, 2009, 2010,
;; 2011 Free Software Foundation, Inc.
;; 2011
, 2012
Free Software Foundation, Inc.
;; Contributed by Embecosm on behalf of Adapteva, Inc.
;; This file is part of GCC.
...
...
@@ -2439,6 +2439,24 @@
emit_move_insn (operands
[
0
]
, operands
[
1
]
);
DONE;
})
(define_expand "movmisalign
<mode>
"
[
(set (match_operand:DWV2MODE 0 "nonimmediate_operand" "")
(match_operand:DWV2MODE 1 "general_operand" ""))]
""
{
rtx op00, op01, op10, op11;
op00 = simplify_gen_subreg (
<vmode
_PART
>
mode, operands
[
0
]
,
<MODE>
mode, 0);
op01 = simplify_gen_subreg (
<vmode
_PART
>
mode, operands
[
0
]
,
<MODE>
mode,
UNITS_PER_WORD);
op10 = simplify_gen_subreg (
<vmode
_PART
>
mode, operands
[
1
]
,
<MODE>
mode, 0);
op11 = simplify_gen_subreg (
<vmode
_PART
>
mode, operands
[
1
]
,
<MODE>
mode,
UNITS_PER_WORD);
emit_move_insn (op00, op10);
emit_move_insn (op01, op11);
DONE;
})
(define_insn "nop"
[
(const_int 0)
]
...
...
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