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riscv-gcc-1
Commit 82975c74 by Andrew Stubbs Committed by Andrew Stubbs
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Allow constants in amdgcn extends and truncates 

2019-12-19  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md
	(<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
	Change input predcate to gcn_alu_operand.
	(extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
	Likewise.
	(truncv64di<mode>2): Likewise.
	(truncv64di<mode>2_exec): Likewise.
	(<convop><mode>v64di2): Likewise.
	(<convop><mode>v64di2_exec): Likewise.

From-SVN: r279587
parent 3a4d2bbc
Showing with 24 additions and 12 deletions
gcc/ChangeLog
2019-12-19 Andrew Stubbs <ams@codesourcery.com> 2019-12-19 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md
(<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
Change input predcate to gcn_alu_operand.
(extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
Likewise.
(truncv64di<mode>2): Likewise.
(truncv64di<mode>2_exec): Likewise.
(<convop><mode>v64di2): Likewise.
(<convop><mode>v64di2_exec): Likewise.
2019-12-19 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ... * config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ...
(*plus_carry_dpp_shr_v64si): ... this, and replace all (*plus_carry_dpp_shr_v64si): ... this, and replace all
VEC_1REG_INT_MODE with V64SI. VEC_1REG_INT_MODE with V64SI.
gcc/config/gcn/gcn-valu.md
...@@ -2491,18 +2491,18 @@ ...@@ -2491,18 +2491,18 @@
(truncate "trunc")]) (truncate "trunc")])
(define_insn "<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>" (define_insn "<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
(zero_convert:VEC_ALL1REG_INT_MODE (zero_convert:VEC_ALL1REG_INT_MODE
(match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))] (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))]
"" ""
"v_mov_b32_sdwa\t%0, %1 dst_sel:<VEC_ALL1REG_INT_MODE:sdwa> dst_unused:UNUSED_PAD src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>" "v_mov_b32_sdwa\t%0, %1 dst_sel:<VEC_ALL1REG_INT_MODE:sdwa> dst_unused:UNUSED_PAD src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
[(set_attr "type" "vop_sdwa") [(set_attr "type" "vop_sdwa")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>" (define_insn "extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
(sign_extend:VEC_ALL1REG_INT_MODE (sign_extend:VEC_ALL1REG_INT_MODE
(match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))] (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))]
"" ""
"v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>" "v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
[(set_attr "type" "vop_sdwa") [(set_attr "type" "vop_sdwa")
...@@ -2515,7 +2515,7 @@ ...@@ -2515,7 +2515,7 @@
(define_insn_and_split "truncv64di<mode>2" (define_insn_and_split "truncv64di<mode>2"
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
(truncate:VEC_ALL1REG_INT_MODE (truncate:VEC_ALL1REG_INT_MODE
(match_operand:V64DI 1 "register_operand" " v")))] (match_operand:V64DI 1 "gcn_alu_operand" " v")))]
"" ""
"#" "#"
"reload_completed" "reload_completed"
...@@ -2536,7 +2536,7 @@ ...@@ -2536,7 +2536,7 @@
[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
(vec_merge:VEC_ALL1REG_INT_MODE (vec_merge:VEC_ALL1REG_INT_MODE
(truncate:VEC_ALL1REG_INT_MODE (truncate:VEC_ALL1REG_INT_MODE
(match_operand:V64DI 1 "register_operand" " v")) (match_operand:V64DI 1 "gcn_alu_operand" " v"))
(match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_or_unspec_operand" (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_or_unspec_operand"
"U0") "U0")
(match_operand:DI 3 "gcn_exec_operand" " e")))] (match_operand:DI 3 "gcn_exec_operand" " e")))]
...@@ -2559,9 +2559,9 @@ ...@@ -2559,9 +2559,9 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn_and_split "<convop><mode>v64di2" (define_insn_and_split "<convop><mode>v64di2"
[(set (match_operand:V64DI 0 "register_operand" "=v") [(set (match_operand:V64DI 0 "register_operand" "=v")
(any_extend:V64DI (any_extend:V64DI
(match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")))] (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v")))]
"" ""
"#" "#"
"reload_completed" "reload_completed"
...@@ -2584,12 +2584,12 @@ ...@@ -2584,12 +2584,12 @@
(set_attr "length" "12")]) (set_attr "length" "12")])
(define_insn_and_split "<convop><mode>v64di2_exec" (define_insn_and_split "<convop><mode>v64di2_exec"
[(set (match_operand:V64DI 0 "register_operand" "=v") [(set (match_operand:V64DI 0 "register_operand" "=v")
(vec_merge:V64DI (vec_merge:V64DI
(any_extend:V64DI (any_extend:V64DI
(match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")) (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v"))
(match_operand:V64DI 2 "gcn_alu_or_unspec_operand" "U0") (match_operand:V64DI 2 "gcn_alu_or_unspec_operand" "U0")
(match_operand:DI 3 "gcn_exec_operand" " e")))] (match_operand:DI 3 "gcn_exec_operand" " e")))]
"" ""
"#" "#"
"reload_completed" "reload_completed"
......
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