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Commit 827555ea by Richard Sandiford Committed by Richard Sandiford
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invoke.texi: Remove the MIPS -membedded-pic option. 

	* doc/invoke.texi: Remove the MIPS -membedded-pic option.
	* config/mips/mips-protos.h (embedded_pic_fnaddr_reg): Delete.
	(embedded_pic_offset): Delete.
	* config/mips/mips.h (MASK_EMBEDDED_PIC): Delete.  Shuffle other
	MASK_* constants.
	(TARGET_EMBEDDED_PIC): Delete.
	(TARGET_SWITCHES): Remove -m{no-,}embedded-pic.
	(ASM_SPEC): Remove -membedded-pic.
	(ASM_OUTPUT_ADDR_DIFF_ELT): Remove embedded-pic handling.
	(ASM_OUTPUT_CASE_LABEL): Likewise.
	* config/mips/vxworks.h (ASM_SPEC): Remove -membedded-pic.
	* config/mips/windiss.h (ASM_SPEC): Likewise.
	* config/mips/mips.c (struct machine_function): Remove
	embedded_pic_fnaddr_rtx.
	(TARGET_ENCODE_SECTION_INFO): Remove override.
	(embedded_pic_fnaddr_reg, embedded_pic_offset): Delete.
	(override_options): Remove -membedded-pic handling.
	(print_operand): Remove handling of '%S'.
	(mips_select_section: Remove -membedded-pic handling.
	(mips_encode_section_info): Delete.
	(mips_output_conditional_branch): Remove mention of -membedded-pic.
	* config/mips/mips.md (define_attr length, movsi, movdi, jump): Remove
	-membedded-pic handling.
	(casesi, casesi_internal, casesi_internal_di, get_fnaddr): Delete.

From-SVN: r81007
parent e930d01a
Showing with 60 additions and 338 deletions
gcc/ChangeLog
2004-04-22 Richard Sandiford <rsandifo@redhat.com>
* doc/invoke.texi: Remove the MIPS -membedded-pic option.
* config/mips/mips-protos.h (embedded_pic_fnaddr_reg): Delete.
(embedded_pic_offset): Delete.
* config/mips/mips.h (MASK_EMBEDDED_PIC): Delete. Shuffle other
MASK_* constants.
(TARGET_EMBEDDED_PIC): Delete.
(TARGET_SWITCHES): Remove -m{no-,}embedded-pic.
(ASM_SPEC): Remove -membedded-pic.
(ASM_OUTPUT_ADDR_DIFF_ELT): Remove embedded-pic handling.
(ASM_OUTPUT_CASE_LABEL): Likewise.
* config/mips/vxworks.h (ASM_SPEC): Remove -membedded-pic.
* config/mips/windiss.h (ASM_SPEC): Likewise.
* config/mips/mips.c (struct machine_function): Remove
embedded_pic_fnaddr_rtx.
(TARGET_ENCODE_SECTION_INFO): Remove override.
(embedded_pic_fnaddr_reg, embedded_pic_offset): Delete.
(override_options): Remove -membedded-pic handling.
(print_operand): Remove handling of '%S'.
(mips_select_section: Remove -membedded-pic handling.
(mips_encode_section_info): Delete.
(mips_output_conditional_branch): Remove mention of -membedded-pic.
* config/mips/mips.md (define_attr length, movsi, movdi, jump): Remove
-membedded-pic handling.
(casesi, casesi_internal, casesi_internal_di, get_fnaddr): Delete.
2004-04-22 Alan Modra <amodra@bigpond.net.au>
* var-tracking.c (frame_base_decl): Remove useless GTY.
......
gcc/config/mips/mips-protos.h
......@@ -117,8 +117,6 @@ extern int m16_nuimm8_4 (rtx, enum machine_mode);
extern int m16_simm8_8 (rtx, enum machine_mode);
extern int m16_nsimm8_8 (rtx, enum machine_mode);
extern struct rtx_def *embedded_pic_fnaddr_reg (void);
extern struct rtx_def *embedded_pic_offset (rtx);
extern rtx mips_subword (rtx, int);
extern bool mips_split_64bit_move_p (rtx, rtx);
extern void mips_split_64bit_move (rtx, rtx);
......
gcc/config/mips/mips.c
......@@ -206,7 +206,6 @@ static void mips_select_rtx_section (enum machine_mode, rtx,
static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
ATTRIBUTE_UNUSED;
static bool mips_in_small_data_p (tree);
static void mips_encode_section_info (tree, rtx, int);
static int mips_fpr_return_fields (tree, tree *);
static bool mips_return_in_msb (tree);
static rtx mips_return_fpr_pair (enum machine_mode mode,
......@@ -274,10 +273,6 @@ struct mips_frame_info GTY(())
};
struct machine_function GTY(()) {
/* Pseudo-reg holding the address of the current function when
generating embedded PIC code. */
rtx embedded_pic_fnaddr_rtx;
/* Pseudo-reg holding the value of $28 in a mips16 function which
refers to GP relative global variables. */
rtx mips16_gp_pseudo_rtx;
......@@ -695,8 +690,6 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mips_address_cost
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
......@@ -2444,55 +2437,6 @@ mips_address_cost (rtx addr)
return mips_address_insns (addr, SImode);
}
/* Return a pseudo that points to the address of the current function.
The first time it is called for a function, an initializer for the
pseudo is emitted in the beginning of the function. */
rtx
embedded_pic_fnaddr_reg (void)
{
if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
{
rtx seq;
cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
/* Output code at function start to initialize the pseudo-reg. */
/* ??? We used to do this in FINALIZE_PIC, but that does not work for
inline functions, because it is called after RTL for the function
has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
does not get copied, and ends up not matching the rest of the RTL.
This solution works, but means that we get unnecessary code to
initialize this value every time a function is inlined into another
function. */
start_sequence ();
emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
XEXP (DECL_RTL (current_function_decl), 0)));
seq = get_insns ();
end_sequence ();
push_topmost_sequence ();
emit_insn_after (seq, get_insns ());
pop_topmost_sequence ();
}
return cfun->machine->embedded_pic_fnaddr_rtx;
}
/* Return RTL for the offset from the current function to the argument.
X is the symbol whose offset from the current function we want. */
rtx
embedded_pic_offset (rtx x)
{
/* Make sure it is emitted. */
embedded_pic_fnaddr_reg ();
return
gen_rtx_CONST (Pmode,
gen_rtx_MINUS (Pmode, x,
XEXP (DECL_RTL (current_function_decl), 0)));
}
/* Return one word of double-word value OP, taking into account the fixed
endianness of certain registers. HIGH_P is true to select the high part,
false to select the low part. */
......@@ -4778,30 +4722,6 @@ override_options (void)
if (!targetm.have_named_sections)
mips_section_threshold = 0;
/* -membedded-pic is a form of PIC code suitable for embedded
systems. All calls are made using PC relative addressing, and
all data is addressed using the $gp register. This requires gas,
which does most of the work, and GNU ld, which automatically
expands PC relative calls which are out of range into a longer
instruction sequence. All gcc really does differently is
generate a different sequence for a switch. */
if (TARGET_EMBEDDED_PIC)
{
flag_pic = 1;
if (TARGET_ABICALLS)
warning ("-membedded-pic and -mabicalls are incompatible");
if (g_switch_set)
warning ("-G and -membedded-pic are incompatible");
/* Setting mips_section_threshold is not required, because gas
will force everything to be GP addressable anyhow, but
setting it will cause gcc to make better estimates of the
number of instructions required to access a particular data
item. */
mips_section_threshold = 0x7fffffff;
}
/* mips_split_addresses is a half-way house between explicit
relocations and the traditional assembler macros. It can
split absolute 32-bit symbolic constants into a high/lo_sum
......@@ -5255,7 +5175,6 @@ mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
'F' print part of opcode for a floating-point branch condition.
'N' print part of opcode for a branch condition, inverted.
'W' print part of opcode for a floating-point branch condition, inverted.
'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
'B' print 'z' for EQ, 'n' for NE
'b' print 'n' for EQ, 'z' for NE
'T' print 'f' for EQ, 't' for NE
......@@ -5493,14 +5412,6 @@ print_operand (FILE *file, rtx op, int letter)
else if (letter == 'R')
print_operand_reloc (file, op, mips_lo_relocs);
else if (letter == 'S')
{
char buffer[100];
ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
assemble_name (file, buffer);
}
else if (letter == 'Z')
{
register int regnum;
......@@ -7260,11 +7171,7 @@ static void
mips_select_section (tree decl, int reloc,
unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
{
if (TARGET_EMBEDDED_PIC && TREE_CODE (decl) == STRING_CST)
/* For embedded position independent code, put constant strings in the
text section, because the data section is limited to 64K in size. */
text_section ();
else if (targetm.have_named_sections)
if (targetm.have_named_sections)
default_elf_select_section (decl, reloc, align);
else
/* The native irix o32 assembler doesn't support named sections. */
......@@ -7318,38 +7225,6 @@ mips_in_small_data_p (tree decl)
size = int_size_in_bytes (TREE_TYPE (decl));
return (size > 0 && size <= mips_section_threshold);
}
/* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
symbols which are not in the .text section. */
static void
mips_encode_section_info (tree decl, rtx rtl, int first)
{
rtx symbol;
if (GET_CODE (rtl) != MEM)
return;
symbol = XEXP (rtl, 0);
if (GET_CODE (symbol) != SYMBOL_REF)
return;
if (TARGET_EMBEDDED_PIC)
{
if (TREE_CODE (decl) == VAR_DECL)
SYMBOL_REF_FLAG (symbol) = 1;
else if (TREE_CODE (decl) == FUNCTION_DECL)
SYMBOL_REF_FLAG (symbol) = 0;
else if (TREE_CODE (decl) == STRING_CST)
SYMBOL_REF_FLAG (symbol) = 0;
else
SYMBOL_REF_FLAG (symbol) = 1;
}
default_encode_section_info (decl, rtl, first);
}
/* See whether VALTYPE is a record whose fields should be returned in
floating-point registers. If so, return the number of fields and
......@@ -8977,7 +8852,7 @@ mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
.set macro
.set reorder
When generating non-embedded PIC, instead of:
When generating PIC, instead of:
j target
......
gcc/config/mips/mips.h
......@@ -154,24 +154,23 @@ extern const struct mips_cpu_info *mips_tune_info;
#define MASK_XGOT 0x00000800 /* emit big-got PIC */
#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
#define MASK_EMBEDDED_DATA 0x00004000 /* Reduce RAM usage, not fast code */
#define MASK_BIG_ENDIAN 0x00008000 /* Generate big endian code */
#define MASK_SINGLE_FLOAT 0x00010000 /* Only single precision FPU. */
#define MASK_MAD 0x00020000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00040000 /* Work-around early Vr4300 CPU bug */
#define MASK_MIPS16 0x00080000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV \
0x00200000 /* divide by zero checking */
#define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
0x00100000 /* divide by zero checking */
#define MASK_BRANCHLIKELY 0x00200000 /* Generate Branch Likely
instructions. */
#define MASK_UNINIT_CONST_IN_RODATA \
0x00800000 /* Store uninitialized
0x00400000 /* Store uninitialized
consts in rodata */
#define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
#define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */
#define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
#define MASK_FIX_VR4120 0x08000000 /* Work around VR4120 errata. */
#define MASK_FIX_R4000 0x00800000 /* Work around R4000 errata. */
#define MASK_FIX_R4400 0x01000000 /* Work around R4400 errata. */
#define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
#define MASK_FIX_VR4120 0x04000000 /* Work around VR4120 errata. */
#define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
......@@ -220,10 +219,6 @@ extern const struct mips_cpu_info *mips_tune_info;
/* always call through a register */
#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
/* generate embedded PIC code;
requires gas. */
#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
/* for embedded systems, optimize for
reduced RAM space instead of for
fastest code. */
......@@ -567,10 +562,6 @@ extern const struct mips_cpu_info *mips_tune_info;
N_("Use indirect calls")}, \
{"no-long-calls", -MASK_LONG_CALLS, \
N_("Don't use indirect calls")}, \
{"embedded-pic", MASK_EMBEDDED_PIC, \
N_("Use embedded PIC")}, \
{"no-embedded-pic", -MASK_EMBEDDED_PIC, \
N_("Don't use embedded PIC")}, \
{"embedded-data", MASK_EMBEDDED_DATA, \
N_("Use ROM instead of RAM")}, \
{"no-embedded-data", -MASK_EMBEDDED_DATA, \
......@@ -1130,7 +1121,6 @@ extern const struct mips_cpu_info *mips_tune_info;
%{mfix-vr4120} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{membedded-pic} \
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
......@@ -3213,19 +3203,15 @@ while (0)
LOCAL_LABEL_PREFIX, \
VALUE)
/* This is how to output an element of a case-vector that is relative.
This is used for pc-relative code (e.g. when TARGET_ABICALLS or
TARGET_EMBEDDED_PIC). */
/* This is how to output an element of a case-vector. We can make the
entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
is supported. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_MIPS16) \
fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_EMBEDDED_PIC) \
fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_GPWORD) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
ptr_mode == DImode ? ".gpdword" : ".gpword", \
......@@ -3236,16 +3222,15 @@ do { \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
/* When generating embedded PIC or mips16 code we want to put the jump
table in the .text section. In all other cases, we want to put the
jump table in the .rdata section. Unfortunately, we can't use
JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
section if appropriate. */
/* When generating mips16 code we want to put the jump table in the .text
section. In all other cases, we want to put the jump table in the .rdata
section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
to the .text section if appropriate. */
#undef ASM_OUTPUT_CASE_LABEL
#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
do { \
if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
if (TARGET_MIPS16) \
function_section (current_function_decl); \
(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
} while (0)
......
gcc/config/mips/mips.md
......@@ -173,8 +173,7 @@
(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
(const_int 131072))
(const_int 4)
(ne (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
(const_int 0))
(ne (symbol_ref "flag_pic") (const_int 0))
(const_int 24)
] (const_int 12))
......@@ -4519,23 +4518,6 @@ dsrl\t%3,%3,1\n\
{
if (mips_legitimize_move (DImode, operands[0], operands[1]))
DONE;
/* If we are generating embedded PIC code, and we are referring to a
symbol in the .text section, we must use an offset from the start
of the function. */
if (TARGET_EMBEDDED_PIC
&& (GET_CODE (operands[1]) == LABEL_REF
|| (GET_CODE (operands[1]) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (operands[1]))))
{
rtx temp;
temp = embedded_pic_offset (operands[1]);
temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
force_reg (DImode, temp));
emit_move_insn (operands[0], force_reg (DImode, temp));
DONE;
}
})
;; For mips16, we need a special case to handle storing $31 into
......@@ -4663,23 +4645,6 @@ dsrl\t%3,%3,1\n\
{
if (mips_legitimize_move (SImode, operands[0], operands[1]))
DONE;
/* If we are generating embedded PIC code, and we are referring to a
symbol in the .text section, we must use an offset from the start
of the function. */
if (TARGET_EMBEDDED_PIC
&& (GET_CODE (operands[1]) == LABEL_REF
|| (GET_CODE (operands[1]) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (operands[1]))))
{
rtx temp;
temp = embedded_pic_offset (operands[1]);
temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
force_reg (SImode, temp));
emit_move_insn (operands[0], force_reg (SImode, temp));
DONE;
}
})
;; We can only store $ra directly into a small sp offset.
......@@ -8091,7 +8056,7 @@ srl\t%M0,%M1,%2\n\
(label_ref (match_operand 0 "" "")))]
"!TARGET_MIPS16"
{
if (flag_pic && ! TARGET_EMBEDDED_PIC)
if (flag_pic)
{
if (get_attr_length (insn) <= 8)
return "%*b\t%l0%/";
......@@ -8107,12 +8072,11 @@ srl\t%M0,%M1,%2\n\
[(set_attr "type" "jump")
(set_attr "mode" "none")
(set (attr "length")
;; we can't use `j' when emitting non-embedded PIC, so we emit
;; branch, if it's in range, or load the address of the branch
;; target into $at in a PIC-compatible way and then jump to it.
;; We can't use `j' when emitting PIC. Emit a branch if it's
;; in range, otherwise load the address of the branch target into
;; $at and then jump to it.
(if_then_else
(ior (eq (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
(const_int 0))
(ior (eq (symbol_ref "flag_pic") (const_int 0))
(lt (abs (minus (match_dup 0)
(plus (pc) (const_int 4))))
(const_int 131072)))
......@@ -8247,107 +8211,6 @@ srl\t%M0,%M1,%2\n\
DONE;
})
;; Implement a switch statement when generating embedded PIC code.
;; Switches are implemented by `tablejump' when not using -membedded-pic.
(define_expand "casesi"
[(set (match_dup 5)
(minus:SI (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" "")))
(set (cc0)
(compare:CC (match_dup 5)
(match_operand:SI 2 "arith_operand" "")))
(set (pc)
(if_then_else (gtu (cc0)
(const_int 0))
(label_ref (match_operand 4 "" ""))
(pc)))
(parallel
[(set (pc)
(mem:SI (plus:SI (mult:SI (match_dup 5)
(const_int 4))
(label_ref (match_operand 3 "" "")))))
(clobber (match_scratch:SI 6 ""))
(clobber (reg:SI 31))])]
"TARGET_EMBEDDED_PIC"
{
rtx index;
/* If the index is too large, go to the default label. */
index = expand_binop (SImode, sub_optab, operands[0],
operands[1], 0, 0, OPTAB_WIDEN);
emit_insn (gen_cmpsi (index, operands[2]));
emit_insn (gen_bgtu (operands[4]));
/* Do the PIC jump. */
if (Pmode != DImode)
emit_jump_insn (gen_casesi_internal (index, operands[3],
gen_reg_rtx (SImode)));
else
emit_jump_insn (gen_casesi_internal_di (index, operands[3],
gen_reg_rtx (DImode)));
DONE;
})
;; An embedded PIC switch statement looks like this:
;; bal $LS1
;; sll $reg,$index,2
;; $LS1:
;; addu $reg,$reg,$31
;; lw $reg,$L1-$LS1($reg)
;; addu $reg,$reg,$31
;; j $reg
;; $L1:
;; .word case1-$LS1
;; .word case2-$LS1
;; ...
(define_insn "casesi_internal"
[(set (pc)
(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
(const_int 4))
(label_ref (match_operand 1 "" "")))))
(clobber (match_operand:SI 2 "register_operand" "=d"))
(clobber (reg:SI 31))]
"TARGET_EMBEDDED_PIC"
{
if (set_nomacro)
return "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
.set macro\;lw\\t%2,%1-%S1(%2)\;.set nomacro\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/";
return
"%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
;
}
[(set_attr "type" "jump")
(set_attr "mode" "none")
(set_attr "length" "24")])
;; This code assumes that the table index will never be >= 29 bits wide,
;; which allows the 'sign extend' from SI to DI be a no-op.
(define_insn "casesi_internal_di"
[(set (pc)
(mem:DI (plus:DI (sign_extend:DI
(mult:SI (match_operand:SI 0 "register_operand" "d")
(const_int 8)))
(label_ref (match_operand 1 "" "")))))
(clobber (match_operand:DI 2 "register_operand" "=d"))
(clobber (reg:DI 31))]
"TARGET_EMBEDDED_PIC"
{
if (set_nomacro)
return "%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
.set macro\;ld\\t%2,%1-%S1(%2)\;.set nomacro\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/";
return
"%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
;
}
[(set_attr "type" "jump")
(set_attr "mode" "none")
(set_attr "length" "24")])
;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
;; While it is possible to either pull it off the stack (in the
;; o32 case) or recalculate it given t9 and our target label,
......@@ -8461,20 +8324,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
[(set_attr "type" "jump")
(set_attr "mode" "none")])
;; When generating embedded PIC code we need to get the address of the
;; current function. This specialized instruction does just that.
(define_insn "get_fnaddr"
[(set (match_operand 0 "register_operand" "=d")
(unspec [(match_operand 1 "" "")] UNSPEC_GET_FNADDR))
(clobber (reg:SI 31))]
"TARGET_EMBEDDED_PIC
&& GET_CODE (operands[1]) == SYMBOL_REF"
"%($LF%= = . + 8\;bal\t$LF%=\;nop;la\t%0,%1-$LF%=%)\;addu\t%0,%0,$31"
[(set_attr "type" "call")
(set_attr "mode" "none")
(set_attr "length" "20")])
;; This is used in compiling the unwind routines.
(define_expand "eh_return"
[(use (match_operand 0 "general_operand" ""))]
......
gcc/config/mips/vxworks.h
......@@ -45,7 +45,6 @@ Boston, MA 02111-1307, USA. */
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{membedded-pic} \
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
......
gcc/config/mips/windiss.h
......@@ -45,7 +45,6 @@ Boston, MA 02111-1307, USA. */
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{membedded-pic} \
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
......
gcc/doc/invoke.texi
......@@ -468,9 +468,9 @@ in the following sections.
@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
-mxgot -mno-xgot -membedded-pic -mno-embedded-pic @gol
-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol
-msingle-float -mdouble-float -mint64 -mlong64 -mlong32 @gol
-mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfp64 @gol
-mhard-float -msoft-float -msingle-float -mdouble-float @gol
-mint64 -mlong64 -mlong32 @gol
-G@var{num} -membedded-data -mno-embedded-data @gol
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
-msplit-addresses -mno-split-addresses @gol
......@@ -7924,16 +7924,6 @@ file accesses more than 64k's worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position
independent code.
@item -membedded-pic
@itemx -mno-embedded-pic
@opindex membedded-pic
@opindex mno-embedded-pic
Generate (do not generate) position-independent code suitable for some
embedded systems. All calls are made using PC relative addresses, and
all data is addressed using the $gp register. No more than 65536
bytes of global data may be used. This requires GNU as and GNU ld,
which do most of the work.
@item -mgp32
@opindex mgp32
Assume that general-purpose registers are 32 bits wide.
......
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