Support scheduling for ColdFire V1 and V3 microarchitecture.

	Improve scheduling of multiplication instructions.

	* config/m68k/m68k.md (cpu): Add cfv1 and cfv3.  Rename cf_v2 to cfv1.
	(mac): New instruction attribute.
	* config/m68k/m68k.c (override_options): Handle cfv1, cfv3 and mac.
	(m68k_sched_mac): New variable.
	(m68k_sched_attr_type2, m68k_sched_md_init_global): Update.
	Handle cfv1 and cfv3.
	(max_insn_size): New static variable.
	(struct _sched_ib): New type.
	(sched_ib): New static variable.
	(sched_ib_size, sched_ib_filled, sched_ib_insn): Convert variables
	to fields of 'struct _sched_ib sched_ib'.  Update all uses.
	(m68k_sched_variable_issue): Add modeling of cfv3 instruction buffer.
	Update.
	(m68k_sched_md_init_global, m68k_sched_md_finish_global,
	m68k_sched_md_init, m68k_sched_md_finish): Handle cfv1 and cfv3.  Init
	new variables.  Update.
	(m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle):
	Add modeling of cfv3 instruction buffer.  Update.
	* config/m68k/m68k-protos.h (m68k_sched_mac): Declare.
	* config/m68k/m68k.h (TUNE_CFV3): New macro.
	* config/m68k/cf.md: Change substrings 'cf_v2' to 'cfv12' or 'cfv123'.
	(cf_* reservations): Rename to cfv12 or cfv123 to indicate cores
	a particular reservation applies to.
	(type2): Reorganize attribute values.  Rename alu to alu_reg,
	alu_l to alu, move_l to omove.  Join move to alu.  Split mul
	to mul_l and mul_w.
	(cf_ib_*): Simplify description of instruction buffer.
	(cf_ib_w0, cf_ib_w4, cf_ib_w5, cf_ib_w6): Remove.
	(cf_mem): Split into cf_mem1 and cf_mem2.
	(cf_v2_move_??): Rename to cfv12_alu_??.
	(cf_v2_move_l_??): Rename to cfv12_omove_??.
	(cf_v2_mul_??): Remove reservations.
	(cfv12_mul_l_??, cfv12_mul_w_??, cfv12_mac_w_??, cfv12_mac_l_??,
	cfv12_emac_??, cfv12_emac_w_i0): New reservations.
	(cfv12_rts, cfv12_call, cfv12_bcc, cfv12_bra, cfv12_jmp): Move to
	appropriate place.
	(cfv3_alu_10, cfv3_omove_10, cfv3_alu_i0, cfv3_omove_i0, cfv3_alu_01,
	cfv3_alu_0i, cfv3_alu_11, cfv3_omove_11, cfv3_alu_i1, cfv3_omove_i1,
	cfv3_alu_1i, cfv3_omove_1i, cfv3_pea_11, cfv3_pea_i1, cfv3_mul_w_10,
	cfv3_mul_l_10, cfv3_mul_w_i0, cfv3_mac_w_10, cfv3_mac_l_10,
	cfv3_mac_w_i0, cfv3_emac_10, cfv3_emac_w_i0, cfv3_rts, cfv3_call,
	cfv3_bcc, cfv3_bra, cfv3_jmp): New reservations.
	(cfv3_*_1, cfv3_*_2, cfv3_*_3): New instruction reservations that are
	expansions of the above reservations for instructions of sizes
	1, 2 and 3 words.

From-SVN: r134552

gcc/ChangeLog

 2008-04-22  Maxim Kuvyrkov  <maxim@codesourcery.com>
 
+	Support scheduling for ColdFire V1 and V3 microarchitecture.
+	Improve scheduling of multiplication instructions.
+
+	* config/m68k/m68k.md (cpu): Add cfv1 and cfv3.  Rename cf_v2 to cfv1.
+	(mac): New instruction attribute.
+	* config/m68k/m68k.c (override_options): Handle cfv1, cfv3 and mac.
+	(m68k_sched_mac): New variable.
+	(m68k_sched_attr_type2, m68k_sched_md_init_global): Update.
+	Handle cfv1 and cfv3.
+	(max_insn_size): New static variable.
+	(struct _sched_ib): New type.
+	(sched_ib): New static variable.
+	(sched_ib_size, sched_ib_filled, sched_ib_insn): Convert variables
+	to fields of 'struct _sched_ib sched_ib'.  Update all uses.
+	(m68k_sched_variable_issue): Add modeling of cfv3 instruction buffer.
+	Update.
+	(m68k_sched_md_init_global, m68k_sched_md_finish_global,
+	m68k_sched_md_init, m68k_sched_md_finish): Handle cfv1 and cfv3.  Init
+	new variables.  Update.
+	(m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle):
+	Add modeling of cfv3 instruction buffer.  Update.
+	* config/m68k/m68k-protos.h (m68k_sched_mac): Declare.
+	* config/m68k/m68k.h (TUNE_CFV3): New macro.
+	* config/m68k/cf.md: Change substrings 'cf_v2' to 'cfv12' or 'cfv123'.
+	(cf_* reservations): Rename to cfv12 or cfv123 to indicate cores
+	a particular reservation applies to.
+	(type2): Reorganize attribute values.  Rename alu to alu_reg,
+	alu_l to alu, move_l to omove.  Join move to alu.  Split mul
+	to mul_l and mul_w.
+	(cf_ib_*): Simplify description of instruction buffer.
+	(cf_ib_w0, cf_ib_w4, cf_ib_w5, cf_ib_w6): Remove.
+	(cf_mem): Split into cf_mem1 and cf_mem2.
+	(cf_v2_move_??): Rename to cfv12_alu_??.
+	(cf_v2_move_l_??): Rename to cfv12_omove_??.
+	(cf_v2_mul_??): Remove reservations.
+	(cfv12_mul_l_??, cfv12_mul_w_??, cfv12_mac_w_??, cfv12_mac_l_??,
+	cfv12_emac_??, cfv12_emac_w_i0): New reservations.
+	(cfv12_rts, cfv12_call, cfv12_bcc, cfv12_bra, cfv12_jmp): Move to
+	appropriate place.
+	(cfv3_alu_10, cfv3_omove_10, cfv3_alu_i0, cfv3_omove_i0, cfv3_alu_01,
+	cfv3_alu_0i, cfv3_alu_11, cfv3_omove_11, cfv3_alu_i1, cfv3_omove_i1,
+	cfv3_alu_1i, cfv3_omove_1i, cfv3_pea_11, cfv3_pea_i1, cfv3_mul_w_10,
+	cfv3_mul_l_10, cfv3_mul_w_i0, cfv3_mac_w_10, cfv3_mac_l_10,
+	cfv3_mac_w_i0, cfv3_emac_10, cfv3_emac_w_i0, cfv3_rts, cfv3_call,
+	cfv3_bcc, cfv3_bra, cfv3_jmp): New reservations.
+	(cfv3_*_1, cfv3_*_2, cfv3_*_3): New instruction reservations that are
+	expansions of the above reservations for instructions of sizes
+	1, 2 and 3 words.
+
+2008-04-22  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
 	* rtl-factoring.c (collect_patterns_seqs): Handle CC0 targets.
 
 2008-04-21  Adam Nemet  <anemet@caviumnetworks.com>

gcc/config/m68k/m68k-protos.h

@@ -67,6 +67,7 @@ extern const char *m68k_output_movem (rtx *, rtx, HOST_WIDE_INT, bool);
 
 #ifdef HAVE_ATTR_cpu
 extern enum attr_cpu m68k_sched_cpu;
+extern enum attr_mac m68k_sched_mac;
 
 extern enum attr_opx_type m68k_sched_attr_opx_type (rtx, int);
 extern enum attr_opy_type m68k_sched_attr_opy_type (rtx, int);

gcc/config/m68k/m68k.c

@@ -666,8 +666,12 @@ override_options (void)
   SUBTARGET_OVERRIDE_OPTIONS;
 
   /* Setup scheduling options.  */
-  if (TUNE_CFV2)
-    m68k_sched_cpu = CPU_CF_V2;
+  if (TUNE_CFV1)
+    m68k_sched_cpu = CPU_CFV1;
+  else if (TUNE_CFV2)
+    m68k_sched_cpu = CPU_CFV2;
+  else if (TUNE_CFV3)
+    m68k_sched_cpu = CPU_CFV3;
   else
     {
       m68k_sched_cpu = CPU_UNKNOWN;
@@ -675,6 +679,16 @@ override_options (void)
       flag_schedule_insns_after_reload = 0;
       flag_modulo_sched = 0;
     }
+
+  if (m68k_sched_cpu != CPU_UNKNOWN)
+    {
+      if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
+	m68k_sched_mac = MAC_CF_EMAC;
+      else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
+	m68k_sched_mac = MAC_CF_MAC;
+      else
+	m68k_sched_mac = MAC_NO;
+    }
 }
 
 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
@@ -4556,6 +4570,9 @@ m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
 /* CPU to schedule the program for.  */
 enum attr_cpu m68k_sched_cpu;
 
+/* MAC to schedule the program for.  */
+enum attr_mac m68k_sched_mac;
+
 /* Operand type.  */
 enum attr_op_type
   {
@@ -5011,14 +5028,14 @@ m68k_sched_attr_type2 (rtx insn)
 {
   switch (get_attr_type1 (insn))
     {
-    case TYPE1_ALU_REG1:
-    case TYPE1_ALU_REGX:
-      return TYPE2_ALU;
-
     case TYPE1_ALU_L:
     case TYPE1_ALUQ_L:
     case TYPE1_CMP_L:
-      return TYPE2_ALU_L;
+      return TYPE2_ALU;
+
+    case TYPE1_ALU_REG1:
+    case TYPE1_ALU_REGX:
+      return TYPE2_ALU_REG;
 
     case TYPE1_BCC:
       return TYPE2_BCC;
@@ -5041,15 +5058,29 @@ m68k_sched_attr_type2 (rtx insn)
     case TYPE1_MOVE:
     case TYPE1_MOVEQ_L:
     case TYPE1_TST:
-      return TYPE2_MOVE;
+      switch (m68k_sched_cpu)
+	{
+	case CPU_CFV1:
+	  return TYPE2_OMOVE;
 
-    case TYPE1_MOVE_L:
-    case TYPE1_TST_L:
-      return TYPE2_MOVE_L;
+	case CPU_CFV2:
+	case CPU_CFV3:
+	  return TYPE2_ALU;
+
+	default:
+	  gcc_assert (get_attr_guess (insn) == GUESS_YES);
+	  return TYPE2_UNKNOWN;
+	}
 
-    case TYPE1_MUL_W:
     case TYPE1_MUL_L:
-      return TYPE2_MUL;
+      return TYPE2_MUL_L;
+
+    case TYPE1_MUL_W:
+      return TYPE2_MUL_W;
+
+    case TYPE1_MOVE_L:
+    case TYPE1_TST_L:
+      return TYPE2_OMOVE;
 
     case TYPE1_PEA:
       return TYPE2_PEA;
@@ -5095,14 +5126,39 @@ m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
   return cost;
 }
 
-/* Size of the instruction buffer in words.  */
-static int sched_ib_size;
+/* Maximal length of instruction for current CPU.
+   E.g. it is 3 for any ColdFire core.  */
+static int max_insn_size;
+
+/* Data to model instruction buffer of CPU.  */
+struct _sched_ib
+{
+  /* Size of the instruction buffer in words.  */
+  int size;
+
+  /* Number of filled words in the instruction buffer.  */
+  int filled;
+
+  /* Additional information about instruction buffer for CPUs that have
+     a buffer of instruction records, rather then a plain buffer
+     of instruction words.  */
+  struct _sched_ib_records
+  {
+    /* Size of buffer in records.  */
+    int n_insns;
 
-/* Number of filled words in the instruction buffer.  */
-static int sched_ib_filled;
+    /* Array to hold data on adjustements made to the size of the buffer.  */
+    int *adjust;
 
-/* An insn that reserves (marks empty) one word in the instruction buffer.  */
-static rtx sched_ib_insn;
+    /* Index of the above array.  */
+    int adjust_index;
+  } records;
+
+  /* An insn that reserves (marks empty) one word in the instruction buffer.  */
+  rtx insn;
+};
+
+static struct _sched_ib sched_ib;
 
 /* ID of memory unit.  */
 static int sched_mem_unit_code;
@@ -5121,19 +5177,58 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
 
   if (recog_memoized (insn) >= 0)
     {
-      insn_size = get_attr_size (insn);
+      switch (m68k_sched_cpu)
+	{
+	case CPU_CFV1:
+	case CPU_CFV2:
+	  insn_size = get_attr_size (insn);
+	  break;
+
+	case CPU_CFV3:
+	  insn_size = get_attr_size (insn);
+	  
+	  /* ColdFire V3 and V4 cores have instruction buffers that can
+	     accumulate up to 8 instructions regardless of instructions'
+	     sizes.  So we should take care not to "prefetch" 24 one-word
+	     or 12 two-words instructions.
+	     To model this behavior we temporarily decrease size of the
+	     buffer by (max_insn_size - insn_size) for next 7 instructions.  */
+	  {
+	    int adjust;
+
+	    adjust = max_insn_size - insn_size;
+	    sched_ib.size -= adjust;
+
+	    if (sched_ib.filled > sched_ib.size)
+	      sched_ib.filled = sched_ib.size;
+
+	    sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
+	  }
+
+	  ++sched_ib.records.adjust_index;
+	  if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
+	    sched_ib.records.adjust_index = 0;
+
+	  /* Undo adjustement we did 7 instructions ago.  */
+	  sched_ib.size
+	    += sched_ib.records.adjust[sched_ib.records.adjust_index];
+
+	  break;
 
-      gcc_assert (insn_size <= sched_ib_filled);
+	default:
+	  gcc_unreachable ();
+	}
 
+      gcc_assert (insn_size <= sched_ib.filled);
       --can_issue_more;
     }
   else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
 	   || asm_noperands (PATTERN (insn)) >= 0)
-    insn_size = sched_ib_filled;
+    insn_size = sched_ib.filled;
   else
     insn_size = 0;
 
-  sched_ib_filled -= insn_size;
+  sched_ib.filled -= insn_size;
 
   return can_issue_more;
 }
@@ -5357,7 +5452,7 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
       m68k_sched_dump (sched_dump_split_class, "m68k_sched_split",
 		       sched_dump);
 
-      sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_v2_guess");
+      sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_guess");
       sched_dump_dfa_state = alloca (state_size ());
 
       m68k_sched_dump (sched_dump_dfa_class, "m68k_sched_dfa",
@@ -5370,21 +5465,32 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
   /* Setup target cpu.  */
   switch (m68k_sched_cpu)
     {
-    case CPU_CF_V2:
-      sched_ib_size = 6;
-      sched_mem_unit_code = get_cpu_unit_code ("cf_v2_mem");
+    case CPU_CFV1:
+    case CPU_CFV2:
+      max_insn_size = 3;
+      sched_ib.records.n_insns = 0;
+      sched_ib.records.adjust = NULL;
+      break;
+
+    case CPU_CFV3:
+      max_insn_size = 3;
+      sched_ib.records.n_insns = 8;
+      sched_ib.records.adjust = xmalloc (sched_ib.records.n_insns
+					 * sizeof (*sched_ib.records.adjust));
       break;
 
     default:
       gcc_unreachable ();
     }
 
+  sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
+
   sched_adjust_cost_state = xmalloc (state_size ());
   state_reset (sched_adjust_cost_state);
 
   start_sequence ();
   emit_insn (gen_ib ());
-  sched_ib_insn = get_insns ();
+  sched_ib.insn = get_insns ();
   end_sequence ();
 }
 
@@ -5393,13 +5499,17 @@ static void
 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
 			     int verbose ATTRIBUTE_UNUSED)
 {
-  sched_ib_insn = NULL;
+  sched_ib.insn = NULL;
 
   free (sched_adjust_cost_state);
   sched_adjust_cost_state = NULL;
 
   sched_mem_unit_code = 0;
-  sched_ib_size = 0;
+
+  free (sched_ib.records.adjust);
+  sched_ib.records.adjust = NULL;
+  sched_ib.records.n_insns = 0;
+  max_insn_size = 0;
 
   free (sched_branch_type);
   sched_branch_type = NULL;
@@ -5413,9 +5523,28 @@ m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
 		    int sched_verbose ATTRIBUTE_UNUSED,
 		    int n_insns ATTRIBUTE_UNUSED)
 {
+  switch (m68k_sched_cpu)
+    {
+    case CPU_CFV1:
+    case CPU_CFV2:
+      sched_ib.size = 6;
+      break;
+
+    case CPU_CFV3:
+      sched_ib.size = sched_ib.records.n_insns * max_insn_size;
+
+      memset (sched_ib.records.adjust, 0,
+	      sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
+      sched_ib.records.adjust_index = 0;
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
   /* haifa-sched.c: schedule_block () calls advance_cycle () just before
      the first cycle.  Workaround that.  */
-  sched_ib_filled = -2;
+  sched_ib.filled = -2;
 }
 
 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
@@ -5426,10 +5555,10 @@ m68k_sched_dfa_pre_advance_cycle (void)
 {
   if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
     {
-      sched_ib_filled += 2;
+      sched_ib.filled += 2;
 
-      if (sched_ib_filled > sched_ib_size)
-	sched_ib_filled = sched_ib_size;
+      if (sched_ib.filled > sched_ib.size)
+	sched_ib.filled = sched_ib.size;
     }
 }
 
@@ -5442,13 +5571,14 @@ static void
 m68k_sched_dfa_post_advance_cycle (void)
 {
   int i;
-  int n;
 
   /* Setup number of prefetched instruction words in the instruction
      buffer.  */
-  for (i = sched_ib_filled, n = sched_ib_size; i < n; ++i)
+  i = max_insn_size - sched_ib.filled;
+
+  while (--i >= 0)
     {
-      if (state_transition (curr_state, sched_ib_insn) >= 0)
+      if (state_transition (curr_state, sched_ib.insn) >= 0)
 	gcc_unreachable ();
     }
 }

gcc/config/m68k/m68k.h

@@ -266,6 +266,7 @@ along with GCC; see the file COPYING3.  If not see
 #define TUNE_CPU32	(m68k_tune == ucpu32)
 #define TUNE_CFV1       (m68k_tune == ucfv1)
 #define TUNE_CFV2	(m68k_tune == ucfv2)
+#define TUNE_CFV3       (m68k_tune == ucfv3)
 
 #define OVERRIDE_OPTIONS   override_options()
 

gcc/config/m68k/m68k.md

@@ -144,7 +144,12 @@
 ;; ::::::::::::::::::::
 
 ;; Processor type.
-(define_attr "cpu" "cf_v2, unknown" (const (symbol_ref "m68k_sched_cpu")))
+(define_attr "cpu" "cfv1, cfv2, cfv3, unknown"
+  (const (symbol_ref "m68k_sched_cpu")))
+
+;; MAC type.
+(define_attr "mac" "no, cf_mac, cf_emac"
+  (const (symbol_ref "m68k_sched_mac")))
 
 ;; Instruction type.
 ;; Basically, an asm pattern.