Commit 82534f65 by Uros Bizjak Committed by Uros Bizjak

i386.md (movstrict<mode>): Use register_operand predicate for operand 0.

	* config/i386/i386.md (movstrict<mode>): Use register_operand
	predicate for operand 0.  Add expander condition.  Assert that
	operand 0 is a SUBREG RTX.
	(*movstrict<mode>_1): Use register_operand predicate for operand 0.
	Update operand constraints and insn condition.
	(zero_extend<mode>si2_and): Do not call gen_movstrict<mode>.
	(zero_extendqihi2_and): Do not call gen_movstrictqi.
	(*setcc_qi_slp): Use register_operand predicate for operand 0.
	Update operand 0 constraints.
	(setcc_qi_slp splitters): Use register_operand predicate for operand 0.

From-SVN: r273891
parent 49c432df
2019-07-30 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (movstrict<mode>): Use register_operand
predicate for operand 0. Add expander condition. Assert that
operand 0 is a SUBREG RTX.
(*movstrict<mode>_1): Use register_operand predicate for operand 0.
Update operand constraints and insn condition.
(zero_extend<mode>si2_and): Do not call gen_movstrict<mode>.
(zero_extendqihi2_and): Do not call gen_movstrictqi.
(*setcc_qi_slp): Use register_operand predicate for operand 0.
Update operand 0 constraints.
(setcc_qi_slp splitters): Use register_operand predicate for operand 0.
2019-07-29 Jozef Lawrynowicz <jozef.l@mittosystems.com> 2019-07-29 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/msp430.h (DRIVER_SELF_SPECS): Define and emit errors * config/msp430/msp430.h (DRIVER_SELF_SPECS): Define and emit errors
......
...@@ -2786,26 +2786,20 @@ ...@@ -2786,26 +2786,20 @@
(set_attr "bdver1_decode" "double")]) (set_attr "bdver1_decode" "double")])
(define_expand "movstrict<mode>" (define_expand "movstrict<mode>"
[(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) [(set (strict_low_part (match_operand:SWI12 0 "register_operand"))
(match_operand:SWI12 1 "general_operand"))] (match_operand:SWI12 1 "general_operand"))]
"" "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
{ {
if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun)) gcc_assert (SUBREG_P (operands[0]));
if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
FAIL; FAIL;
if (SUBREG_P (operands[0])
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
FAIL;
/* Don't generate memory->memory moves, go through a register */
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}) })
(define_insn "*movstrict<mode>_1" (define_insn "*movstrict<mode>_1"
[(set (strict_low_part [(set (strict_low_part
(match_operand:SWI12 0 "nonimmediate_operand" "+<r>m,<r>")) (match_operand:SWI12 0 "register_operand" "+<r>"))
(match_operand:SWI12 1 "general_operand" "<r>n,m"))] (match_operand:SWI12 1 "general_operand" "<r>mn"))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"mov{<imodesuffix>}\t{%1, %0|%0, %1}" "mov{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
...@@ -4011,8 +4005,10 @@ ...@@ -4011,8 +4005,10 @@
ix86_expand_clear (operands[0]); ix86_expand_clear (operands[0]);
gcc_assert (!TARGET_PARTIAL_REG_STALL); gcc_assert (!TARGET_PARTIAL_REG_STALL);
emit_insn (gen_movstrict<mode> emit_insn (gen_rtx_SET
(gen_lowpart (<MODE>mode, operands[0]), operands[1])); (gen_rtx_STRICT_LOW_PART
(VOIDmode, gen_lowpart (<MODE>mode, operands[0])),
operands[1]));
DONE; DONE;
} }
...@@ -4063,8 +4059,10 @@ ...@@ -4063,8 +4059,10 @@
ix86_expand_clear (operands[0]); ix86_expand_clear (operands[0]);
gcc_assert (!TARGET_PARTIAL_REG_STALL); gcc_assert (!TARGET_PARTIAL_REG_STALL);
emit_insn (gen_movstrictqi emit_insn (gen_rtx_SET
(gen_lowpart (QImode, operands[0]), operands[1])); (gen_rtx_STRICT_LOW_PART
(VOIDmode, gen_lowpart (QImode, operands[0])),
operands[1]));
DONE; DONE;
} }
...@@ -11835,7 +11833,7 @@ ...@@ -11835,7 +11833,7 @@
(set_attr "mode" "QI")]) (set_attr "mode" "QI")])
(define_insn "*setcc_qi_slp" (define_insn "*setcc_qi_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) [(set (strict_low_part (match_operand:QI 0 "register_operand" "+q"))
(match_operator:QI 1 "ix86_comparison_operator" (match_operator:QI 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))] [(reg FLAGS_REG) (const_int 0)]))]
"" ""
...@@ -11864,7 +11862,7 @@ ...@@ -11864,7 +11862,7 @@
}) })
(define_split (define_split
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) [(set (strict_low_part (match_operand:QI 0 "register_operand"))
(ne:QI (match_operator 1 "ix86_comparison_operator" (ne:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]) [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))] (const_int 0)))]
...@@ -11896,7 +11894,7 @@ ...@@ -11896,7 +11894,7 @@
}) })
(define_split (define_split
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) [(set (strict_low_part (match_operand:QI 0 "register_operand"))
(eq:QI (match_operator 1 "ix86_comparison_operator" (eq:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]) [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))] (const_int 0)))]
......
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