Commit 82452399 by Ramana Radhakrishnan Committed by Ramana Radhakrishnan

common.opt (frtl-abstract-sequences): Delete.

2009-03-31  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* common.opt (frtl-abstract-sequences): Delete.
	* doc/invoke.texi (Option Summary): Likewise.
	(Optimize Options): Likewise.
	* rtl-factoring.c: Delete file.
	* Makefile.in (OBJS-common): Remove rtl-factoring.o.
	* passes.c (init_optimization_passes): Remove rtl_abstr_seq pass.


2009-03-31  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gcc.c-torture/compile/pr33009.c: Delete.
	* gcc.c-torture/compile/pr11832.c: Likewise.

From-SVN: r145374
parent 207bf79d
......@@ -1169,7 +1169,6 @@ OBJS-common = \
reorg.o \
resource.o \
rtl-error.o \
rtl-factoring.o \
rtl.o \
rtlanal.o \
rtlhooks.o \
......@@ -2193,10 +2192,6 @@ tree-cfgcleanup.o : tree-cfgcleanup.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \
$(TREE_DUMP_H) $(EXCEPT_H) langhooks.h $(CFGLOOP_H) tree-pass.h \
$(CFGLAYOUT_H) $(BASIC_BLOCK_H) hard-reg-set.h $(HASHTAB_H) $(TOPLEV_H) \
tree-ssa-propagate.h tree-scalar-evolution.h
rtl-factoring.o : rtl-factoring.c $(CONFIG_H) $(SYSTEM_H) $(RTL_H) \
coretypes.h $(TM_H) $(BASIC_BLOCK_H) $(RESOURCE_H) $(GGC_H) $(REGS_H) \
$(PARAMS_H) $(EXPR_H) addresses.h $(TM_P_H) tree-pass.h $(TREE_FLOW_H) \
$(TIMEVAR_H) output.h $(DF_H)
tree-tailcall.o : tree-tailcall.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \
$(RTL_H) $(TREE_H) $(TM_P_H) $(FUNCTION_H) $(TM_H) coretypes.h \
$(TREE_DUMP_H) $(DIAGNOSTIC_H) $(EXCEPT_H) tree-pass.h $(FLAGS_H) langhooks.h \
......
......@@ -1037,10 +1037,6 @@ fsection-anchors
Common Report Var(flag_section_anchors) Optimization
Access data in the same section from shared anchor points
frtl-abstract-sequences
Common Report Var(flag_rtl_seqabstr) Optimization
Perform sequence abstraction optimization on RTL
fsee
Common Report Var(flag_see) Init(0)
Eliminate redundant sign extensions using LCM.
......
......@@ -356,7 +356,7 @@ Objective-C and Objective-C++ Dialects}.
-freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
-frounding-math -frtl-abstract-sequences -fsched2-use-superblocks @gol
-frounding-math -fsched2-use-superblocks @gol
-fsched2-use-traces -fsched-spec-load -fsched-spec-load-dangerous @gol
-fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol
-fschedule-insns -fschedule-insns2 -fsection-anchors -fsee @gol
......@@ -6954,14 +6954,6 @@ Future versions of GCC may provide finer control of this setting
using C99's @code{FENV_ACCESS} pragma. This command line option
will be used to specify the default state for @code{FENV_ACCESS}.
@item -frtl-abstract-sequences
@opindex frtl-abstract-sequences
It is a size optimization method. This option is to find identical
sequences of code, which can be turned into pseudo-procedures and
then replace all occurrences with calls to the newly created
subroutine. It is kind of an opposite of @option{-finline-functions}.
This optimization runs at RTL level.
@item -fsignaling-nans
@opindex fsignaling-nans
Compile code assuming that IEEE signaling NaNs may generate user-visible
......
......@@ -787,7 +787,6 @@ init_optimization_passes (void)
NEXT_PASS (pass_branch_target_load_optimize1);
NEXT_PASS (pass_thread_prologue_and_epilogue);
NEXT_PASS (pass_rtl_dse2);
NEXT_PASS (pass_rtl_seqabstr);
NEXT_PASS (pass_stack_adjustments);
NEXT_PASS (pass_peephole2);
NEXT_PASS (pass_if_after_reload);
......
2009-03-31 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.c-torture/compile/pr33009.c: Delete.
* gcc.c-torture/compile/pr11832.c: Likewise.
2009-03-31 Joseph Myers <joseph@codesourcery.com>
PR c/448
......
/* { dg-do compile } */
/* Currently ICEs for Alpha, IA64, HPPA, MIPS, CRIS, Xtensa, PowerPC, SH and SPARC; see PR33642. */
/* { dg-xfail-if "PR33642" { alpha*-*-* hppa*-*-* mips*-*-* powerpc*-*-* cris-*-* crisv32-*-* ia64-*-* xtensa*-*-* sh*-*-* sparc*-*-* s390*-*-* } { "*" } { "" } } */
/* Currently ICEs for (x86 && ilp32 && pic). */
/* { dg-xfail-if "PR33642/36240" { { i?86-*-* x86_64-*-* } && { ilp32 && { ! nonpic } } } { "*" } { "" } } */
/* { dg-prune-output ".*internal compiler error.*" }
/* { dg-options "-frtl-abstract-sequences" } */
int a, b, e;
unsigned char *c;
void foo()
{
int d = 13;
b = -1;
switch (e) {
case 1:
b++; c[b] = (unsigned char)d;
break;
case 2:
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
break;
case 3:
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
break;
default:
a = 1;
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
b++; c[b] = (unsigned char)d;
}
}
/* { dg-do compile } */
/* Currently ICEs for Alpha, IA64, HPPA, MIPS, CRIS, Xtensa, PowerPC, SH and SPARC; see PR33642. */
/* { dg-xfail-if "PR33642" { alpha*-*-* hppa*-*-* mips*-*-* powerpc*-*-* cris-*-* crisv32-*-* ia64-*-* xtensa*-*-* sh*-*-* sparc*-*-* s390*-*-* } { "*" } { "" } } */
/* Currently ICEs for (x86 && ilp32 && pic). */
/* { dg-xfail-if "PR33642/36240" { { i?86-*-* x86_64-*-* } && { ilp32 && { ! nonpic } } } { "*" } { "" } } */
/* { dg-prune-output ".*internal compiler error.*" }
/* { dg-options "-frtl-abstract-sequences" } */
char *progName;
int bar0 (char *, ...);
void bar1 (char *);
void exit (int);
#define SAME \
bar0 ("%s: Bad flag `%s'\n", argv[i], argv[i] );\
bar1 ( progName ); \
exit ( 1 );
int foo ( int argc, char *argv[] )
{
int i;
for (i = 0; i < argc; i++) {
switch (argv[i][0]) {
case 'c':
break;
default:
SAME
break;
}
}
for (i = 0; i < argc; i++) {
SAME
}
return 0;
}
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