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riscv-gcc-1
Commit 814049be by Walter Lee Committed by Walter Lee
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TILE-Gx: fix clzsi2 for big-endian. 

        * config/tilegx/tilegx.md (clzsi2): Fix for big-endian.

From-SVN: r242616
parent 7a384912
Showing with 18 additions and 13 deletions
gcc/ChangeLog
2016-11-18 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.md (clzsi2): Fix for big-endian.
2016-11-18 Jakub Jelinek <jakub@redhat.com> 2016-11-18 Jakub Jelinek <jakub@redhat.com>
PR middle-end/78419 PR middle-end/78419
gcc/config/tilegx/tilegx.md
...@@ -1798,19 +1798,20 @@ ...@@ -1798,19 +1798,20 @@
[(set_attr "type" "Y0")]) [(set_attr "type" "Y0")])
(define_expand "clzsi2" (define_expand "clzsi2"
[(set (match_dup 2) [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) (clz:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))]
(set (match_dup 2) ""
(ashift:DI (match_dup 2) {
(const_int 32))) rtx tmp1 = gen_reg_rtx (DImode);
(set (match_dup 2) rtx tmp2 = gen_reg_rtx (DImode);
(clz:DI (match_dup 2))) rtx tmp3 = gen_reg_rtx (DImode);
(set (match_operand:SI 0 "register_operand" "")
(subreg:SI (match_dup 2) 0))] emit_insn (gen_zero_extendsidi2 (tmp1, operands[1]));
"" emit_insn (gen_ashldi3 (tmp2, tmp1, (GEN_INT (32))));
{ emit_insn (gen_clzdi2 (tmp3, tmp2));
operands[2] = gen_reg_rtx (DImode); emit_move_insn (operands[0], gen_lowpart (SImode, tmp3));
}) DONE;
})
(define_insn "ctz<mode>2" (define_insn "ctz<mode>2"
[(set (match_operand:I48MODE 0 "register_operand" "=r") [(set (match_operand:I48MODE 0 "register_operand" "=r")
......
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