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riscv-gcc-1
Commit 809e78cc by Richard Henderson Committed by Richard Henderson
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sparc.c (TARGET_TRAMPOLINE_INIT): New. 

        * config/sparc/sparc.c (TARGET_TRAMPOLINE_INIT): New.
        (sparc32_initialize_trampoline): Rename from
        sparc_initialize_trampoline; make static; replace tramp parameter
        with m_tramp and update memory accesses.
        (sparc64_initialize_trampoline): Similarly.
        (sparc_trampoline_init): New.
        * config/sparc/sparc-protos.h: Remove trampoline decls.
        * config/sparc/sparc.h (INITIALIZE_TRAMPOLINE): Remove.
        * config/sparc/sparc.md (nonlocal_goto): Don't use static_chain_rtx.

From-SVN: r152012
parent 994322ef
Showing with 47 additions and 35 deletions
gcc/ChangeLog
......@@ -253,6 +253,16 @@
* config/sh/sh.h (INITIALIZE_TRAMPOLINE): New.
(TRAMPOLINE_ADJUST_ADDRESS): Move code to sh_trampoline_adjust_address.
* config/sparc/sparc.c (TARGET_TRAMPOLINE_INIT): New.
(sparc32_initialize_trampoline): Rename from
sparc_initialize_trampoline; make static; replace tramp parameter
with m_tramp and update memory accesses.
(sparc64_initialize_trampoline): Similarly.
(sparc_trampoline_init): New.
* config/sparc/sparc-protos.h: Remove trampoline decls.
* config/sparc/sparc.h (INITIALIZE_TRAMPOLINE): Remove.
* config/sparc/sparc.md (nonlocal_goto): Don't use static_chain_rtx.
2009-09-22 Jakub Jelinek <jakub@redhat.com>
* config/rs6000/rs6000.c (bdesc_2arg): Fix CODE_FOR_vector_gt* codes
......
gcc/config/sparc/sparc-protos.h
......@@ -61,9 +61,6 @@ extern void sparc_emit_fixunsdi (rtx [2], enum machine_mode);
extern void emit_tfmode_binop (enum rtx_code, rtx *);
extern void emit_tfmode_unop (enum rtx_code, rtx *);
extern void emit_tfmode_cvt (enum rtx_code, rtx *);
/* This function handles all v9 scc insns */
extern void sparc_initialize_trampoline (rtx, rtx, rtx);
extern void sparc64_initialize_trampoline (rtx, rtx, rtx);
extern bool legitimate_constant_p (rtx);
extern bool constant_address_p (rtx);
extern bool legitimate_pic_operand_p (rtx);
......
gcc/config/sparc/sparc.c
......@@ -424,6 +424,7 @@ static bool sparc_can_eliminate (const int, const int);
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
static const char *sparc_mangle_type (const_tree);
#endif
static void sparc_trampoline_init (rtx, tree, rtx);
#ifdef SUBTARGET_ATTRIBUTE_TABLE
/* Table of valid machine attributes. */
......@@ -600,6 +601,9 @@ static bool fpu_option_set = false;
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
struct gcc_target targetm = TARGET_INITIALIZER;
/* Implement TARGET_HANDLE_OPTION. */
......@@ -7404,8 +7408,8 @@ sparc_type_code (register tree type)
Emit enough FLUSH insns to synchronize the data and instruction caches. */
void
sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
static void
sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
{
/* SPARC 32-bit trampoline:
......@@ -7419,7 +7423,7 @@ sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
*/
emit_move_insn
(gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
(adjust_address (m_tramp, SImode, 0),
expand_binop (SImode, ior_optab,
expand_shift (RSHIFT_EXPR, SImode, fnaddr,
size_int (10), 0, 1),
......@@ -7427,7 +7431,7 @@ sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
NULL_RTX, 1, OPTAB_DIRECT));
emit_move_insn
(gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
(adjust_address (m_tramp, SImode, 4),
expand_binop (SImode, ior_optab,
expand_shift (RSHIFT_EXPR, SImode, cxt,
size_int (10), 0, 1),
......@@ -7435,14 +7439,14 @@ sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
NULL_RTX, 1, OPTAB_DIRECT));
emit_move_insn
(gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
(adjust_address (m_tramp, SImode, 8),
expand_binop (SImode, ior_optab,
expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
NULL_RTX, 1, OPTAB_DIRECT));
emit_move_insn
(gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
(adjust_address (m_tramp, SImode, 12),
expand_binop (SImode, ior_optab,
expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
......@@ -7450,19 +7454,18 @@ sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
/* On UltraSPARC a flush flushes an entire cache line. The trampoline is
aligned on a 16 byte boundary so one flush clears it all. */
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
if (sparc_cpu != PROCESSOR_ULTRASPARC
&& sparc_cpu != PROCESSOR_ULTRASPARC3
&& sparc_cpu != PROCESSOR_NIAGARA
&& sparc_cpu != PROCESSOR_NIAGARA2)
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
plus_constant (tramp, 8)))));
emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
/* Call __enable_execute_stack after writing onto the stack to make sure
the stack address is accessible. */
#ifdef ENABLE_EXECUTE_STACK
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
#endif
}
......@@ -7471,8 +7474,8 @@ sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
values as "immediate" data out of the trampoline. It's also easier since
we can read the PC without clobbering a register. */
void
sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
static void
sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
{
/* SPARC 64-bit trampoline:
......@@ -7483,31 +7486,44 @@ sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
+16 bytes data
*/
emit_move_insn (gen_rtx_MEM (SImode, tramp),
emit_move_insn (adjust_address (m_tramp, SImode, 0),
GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
emit_move_insn (adjust_address (m_tramp, SImode, 4),
GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
emit_move_insn (adjust_address (m_tramp, SImode, 8),
GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
emit_move_insn (adjust_address (m_tramp, SImode, 12),
GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
if (sparc_cpu != PROCESSOR_ULTRASPARC
&& sparc_cpu != PROCESSOR_ULTRASPARC3
&& sparc_cpu != PROCESSOR_NIAGARA
&& sparc_cpu != PROCESSOR_NIAGARA2)
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
/* Call __enable_execute_stack after writing onto the stack to make sure
the stack address is accessible. */
#ifdef ENABLE_EXECUTE_STACK
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
#endif
}
/* Worker for TARGET_TRAMPOLINE_INIT. */
static void
sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
{
rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
cxt = force_reg (Pmode, cxt);
if (TARGET_ARCH64)
sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
else
sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
}
/* Adjust the cost of a scheduling dependency. Return the new cost of
a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
......
gcc/config/sparc/sparc.h
......@@ -1612,16 +1612,6 @@ do { \
#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
#define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
/* Emit RTL insns to initialize the variable parts of a trampoline.
FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
if (TARGET_ARCH64) \
sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
else \
sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
/* Generate RTL to flush the register windows so as to make arbitrary frames
available. */
......
gcc/config/sparc/sparc.md
......@@ -6397,7 +6397,6 @@
emit_move_insn (hard_frame_pointer_rtx, stack);
emit_use (stack_pointer_rtx);
emit_use (static_chain_rtx);
/* ??? The V9-specific version was disabled in rev 1.65. */
emit_jump_insn (gen_goto_handler_and_restore (labreg));
......
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