sse.md (vec_extractv4sf): Removed.

2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/sse.md (vec_extractv4sf): Removed.
	(vec_extractv2df): Likewise.
	(vec_extractv2di): Likewise.
	(vec_extractv4si): Likewise.
	(vec_extractv8hi): Likewise.
	(vec_extractv16qi): Likewise.
	(vec_extract<mode>): New.

From-SVN: r135728

gcc/ChangeLog

 2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* config/i386/sse.md (vec_extractv4sf): Removed.
+	(vec_extractv2df): Likewise.
+	(vec_extractv2di): Likewise.
+	(vec_extractv4si): Likewise.
+	(vec_extractv8hi): Likewise.
+	(vec_extractv16qi): Likewise.
+	(vec_extract<mode>): New.
+
+2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* config/i386/sse.md (vec_setv4sf): Removed.
 	(vec_setv2df): Likewise.
 	(vec_setv2di): Likewise.

gcc/config/i386/sse.md

@@ -2429,9 +2429,9 @@
   DONE;
 })
 
-(define_expand "vec_extractv4sf"
-  [(match_operand:SF 0 "register_operand" "")
-   (match_operand:V4SF 1 "register_operand" "")
+(define_expand "vec_extract<mode>"
+  [(match_operand:<ssescalarmode> 0 "register_operand" "")
+   (match_operand:SSEMODE 1 "register_operand" "")
    (match_operand 2 "const_int_operand" "")]
   "TARGET_SSE"
 {
@@ -2786,17 +2786,6 @@
   [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
    (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
 
-(define_expand "vec_extractv2df"
-  [(match_operand:DF 0 "register_operand" "")
-   (match_operand:V2DF 1 "register_operand" "")
-   (match_operand 2 "const_int_operand" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_extract (false, operands[0], operands[1],
-			      INTVAL (operands[2]));
-  DONE;
-})
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel integral arithmetic
@@ -4910,50 +4899,6 @@
   [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,ssemov")
    (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
 
-(define_expand "vec_extractv2di"
-  [(match_operand:DI 0 "register_operand" "")
-   (match_operand:V2DI 1 "register_operand" "")
-   (match_operand 2 "const_int_operand" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_extract (false, operands[0], operands[1],
-			      INTVAL (operands[2]));
-  DONE;
-})
-
-(define_expand "vec_extractv4si"
-  [(match_operand:SI 0 "register_operand" "")
-   (match_operand:V4SI 1 "register_operand" "")
-   (match_operand 2 "const_int_operand" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_extract (false, operands[0], operands[1],
-			      INTVAL (operands[2]));
-  DONE;
-})
-
-(define_expand "vec_extractv8hi"
-  [(match_operand:HI 0 "register_operand" "")
-   (match_operand:V8HI 1 "register_operand" "")
-   (match_operand 2 "const_int_operand" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_extract (false, operands[0], operands[1],
-			      INTVAL (operands[2]));
-  DONE;
-})
-
-(define_expand "vec_extractv16qi"
-  [(match_operand:QI 0 "register_operand" "")
-   (match_operand:V16QI 1 "register_operand" "")
-   (match_operand 2 "const_int_operand" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_extract (false, operands[0], operands[1],
-			      INTVAL (operands[2]));
-  DONE;
-})
-
 (define_expand "vec_unpacku_hi_v16qi"
   [(match_operand:V8HI 0 "register_operand" "")
    (match_operand:V16QI 1 "register_operand" "")]