re PR target/65671 (Assembly failure (invalid register operand) with -O3 -mavx512vl)

	PR target/65671
gcc/
	* config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
	is disabled.

gcc/testsuite/
	* gcc.target/i386/pr65671.c: New.

From-SVN: r221963

gcc/ChangeLog

+2015-04-09  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/65671
+	* config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
+	is disabled.
+
 2015-04-09  Gerald Pfeifer  <gerald@pfeifer.com>
 
 	* doc/contrib.texi (Contributors): Add John Marino.

gcc/config/i386/sse.md

@@ -7015,10 +7015,15 @@
 	(vec_select:<ssehalfvecmode>
 	  (match_operand:VI8F_256 1 "register_operand" "v,v")
 	  (parallel [(const_int 2) (const_int 3)])))]
-  "TARGET_AVX"
+  "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
 {
-  if (TARGET_AVX512DQ && TARGET_AVX512VL)
-    return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
+  if (TARGET_AVX512VL)
+  {
+    if (TARGET_AVX512DQ)
+      return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
+    else
+      return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}";
+  }
   else
     return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
 }

gcc/testsuite/ChangeLog

+2015-04-09  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/65671
+	* gcc.target/i386/pr65671.c: New.
+
 2015-04-09  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/65709

gcc/testsuite/gcc.target/i386/pr65671.c

+/* PR target/65671 */
+/* { dg-do assemble } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx512vl -ffixed-ymm16" } */
+
+#include <x86intrin.h>
+
+register __m256d a asm ("ymm16");
+__m128d b;
+
+void
+foo ()
+{
+  b = _mm256_extractf128_pd (a, 1);
+}