Commit 7efcf910 by Chung-Lin Tang Committed by Chung-Lin Tang

re PR rtl-optimization/46178 (gcc.target/i386/(u)divmod-[58].c FAIL: ICE: in…

re PR rtl-optimization/46178 (gcc.target/i386/(u)divmod-[58].c FAIL: ICE: in dec_register_pressure, at ira-lives.c:215 with -fira-algorithm=priority)

2011-02-18  Chung-Lin Tang  <cltang@codesourcery.com>

	PR rtl-optimization/46178
	* ira.c (setup_hard_regno_class): Use ira_class_translate[] to
	compute ira_hard_regno_cover_class[].

From-SVN: r170277
parent 4a16e681
2011-02-18 Chung-Lin Tang <cltang@codesourcery.com>
PR rtl-optimization/46178
* ira.c (setup_hard_regno_class): Use ira_class_translate[] to
compute ira_hard_regno_cover_class[].
2011-02-18 Richard Guenther <rguenther@suse.de>
PR lto/47798
......
......@@ -1033,22 +1033,14 @@ find_reg_class_closure (void)
static void
setup_hard_regno_cover_class (void)
{
int i, j;
enum reg_class cl;
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
ira_hard_regno_cover_class[i] = NO_REGS;
for (j = 0; j < ira_reg_class_cover_size; j++)
{
cl = ira_reg_class_cover[j];
if (ira_class_hard_reg_index[cl][i] >= 0)
{
ira_hard_regno_cover_class[i] = cl;
break;
}
}
ira_hard_regno_cover_class[i]
= (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
? NO_REGS
: ira_class_translate[REGNO_REG_CLASS (i)]);
}
}
......
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