Commit 7ee72796 by Jeffrey A Law Committed by Jeff Law

pa.c (override_options): Promote -fpic to -fPIC.

        * pa.c (override_options): Promote -fpic to -fPIC.
        (legitimize_pic_address): Simplify due to removal of
        small PIC as a code generation option.
        (secondary_reload_class): Similarly.
        * pa.h (GO_IF_LEGITIMATE_ADDRESS): Similarly.
        (PRINT_OPERAND_ADDRESS): Similarly.
        * pa.md (various patterns): Similarly.
        (small pic lo_sum pattern): Remove.

From-SVN: r40101
parent 9dd3d53c
Tue Feb 27 16:49:13 2001 Jeffrey A Law (law@cygnus.com)
* pa.c (override_options): Promote -fpic to -fPIC.
(legitimize_pic_address): Simplify due to removal of
small PIC as a code generation option.
(secondary_reload_class): Similarly.
* pa.h (GO_IF_LEGITIMATE_ADDRESS): Similarly.
(PRINT_OPERAND_ADDRESS): Similarly.
* pa.md (various patterns): Similarly.
(small pic lo_sum pattern): Remove.
Tue Feb 27 16:01:13 CET 2001 Jan Hubicka <jh@suse.cz>
Fergus Henderson
......
......@@ -183,8 +183,9 @@ override_options ()
write_symbols = NO_DEBUG;
}
/* We always generate PIC code when in 64bit mode. */
if (TARGET_64BIT)
/* We only support the "big PIC" model now. And we always generate PIC
code when in 64bit mode. */
if (flag_pic == 1 || TARGET_64BIT)
flag_pic = 2;
/* Register global variables with the garbage collector. */
......@@ -713,22 +714,15 @@ legitimize_pic_address (orig, mode, reg)
if (reg == 0)
abort ();
if (flag_pic == 2)
{
emit_move_insn (reg,
gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
gen_rtx_HIGH (word_mode, orig)));
pic_ref
= gen_rtx_MEM (Pmode,
gen_rtx_LO_SUM (Pmode, reg,
gen_rtx_UNSPEC (Pmode,
gen_rtvec (1, orig),
0)));
}
else
pic_ref = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
orig));
emit_move_insn (reg,
gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
gen_rtx_HIGH (word_mode, orig)));
pic_ref
= gen_rtx_MEM (Pmode,
gen_rtx_LO_SUM (Pmode, reg,
gen_rtx_UNSPEC (Pmode,
gen_rtvec (1, orig),
0)));
current_function_uses_pic_offset_table = 1;
RTX_UNCHANGING_P (pic_ref) = 1;
......@@ -4564,7 +4558,7 @@ secondary_reload_class (class, mode, in)
/* Trying to load a constant into a FP register during PIC code
generation will require %r1 as a scratch register. */
if (flag_pic == 2
if (flag_pic
&& GET_MODE_CLASS (mode) == MODE_INT
&& FP_REG_CLASS_P (class)
&& (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
......
......@@ -1269,16 +1269,7 @@ extern int may_call_alloca;
else if (GET_CODE (X) == PLUS) \
{ \
rtx base = 0, index = 0; \
if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
{ \
if (GET_CODE (XEXP (X, 1)) == REG \
&& REG_OK_FOR_BASE_P (XEXP (X, 1))) \
goto ADDR; \
else if (flag_pic == 1 \
&& GET_CODE (XEXP (X, 1)) == SYMBOL_REF)\
goto ADDR; \
} \
else if (REG_P (XEXP (X, 0)) \
if (REG_P (XEXP (X, 0)) \
&& REG_OK_FOR_BASE_P (XEXP (X, 0))) \
base = XEXP (X, 0), index = XEXP (X, 1); \
else if (REG_P (XEXP (X, 1)) \
......@@ -1970,9 +1961,7 @@ while (0)
fputs ("R'", FILE); \
else if (flag_pic == 0) \
fputs ("RR'", FILE); \
else if (flag_pic == 1) \
abort (); \
else if (flag_pic == 2) \
else \
fputs ("RT'", FILE); \
output_global_address (FILE, XEXP (addr, 1), 0); \
fputs ("(", FILE); \
......
......@@ -2085,17 +2085,6 @@
DONE;
}")
;;; pic symbol references
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "symbolic_operand" ""))))]
"flag_pic && operands[1] == pic_offset_table_rtx"
"ldw T'%2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
"=r,r,r,r,r,r,Q,*q,!f,f,*TR")
......@@ -2331,7 +2320,7 @@
(high:SI (match_operand 2 "" ""))))]
"symbolic_operand (operands[2], Pmode)
&& ! function_label_operand (operands[2], Pmode)
&& flag_pic == 2"
&& flag_pic"
"addil LT'%G2,%1"
[(set_attr "type" "binary")
(set_attr "length" "4")])
......@@ -2343,7 +2332,7 @@
"symbolic_operand (operands[2], Pmode)
&& ! function_label_operand (operands[2], Pmode)
&& TARGET_64BIT
&& flag_pic == 2"
&& flag_pic"
"addil LT'%G2,%1"
[(set_attr "type" "binary")
(set_attr "length" "4")])
......
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