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riscv-gcc-1
Commit 7ec6356e by Bernd Schmidt Committed by Bernd Schmidt
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arm.c (get_arm_condition_code): Remove CC_NOTBmode case. 

	* config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case.
	* arm-modes.def (CC_NOTB): Don't define.
	* config/arm/arm.md (arm_adddi3): Generate canonical RTL.
	(adddi_sesidi_di, adddi_zesidi_di): Likewise.
	(LTUGEU): New code_iterator.
	(cnb, optab): New corresponding code_attrs.
	(addsi3_carryin_<optab>): Renamed from addsi3_carryin.  Change pattern
	to canonical form.  Operands 1 and 2 are commutative.  Parametrize
	using LTUGEU.
	(addsi3_carryin_shift_<optab>): Likewise.
	(addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2.
	Operands 1 and 2 are commutative.  Parametrize using LTUGEU.
	(addsi3_carryin_alt1, addsi3_carryin_alt3): Remove.
	(subsi3_compare): Renamed from subsi3_compare0_c.  Change CC_NOTB to
	CC.
	(arm_subsi3_insn): Allow constants for operand 0.
	(compare_scc peephole for eq case): New.
	(compare_scc splitters): Change CC_NOTB to CC.

From-SVN: r161831
parent 75421dcd
Showing with 88 additions and 70 deletions
gcc/ChangeLog
2010-07-05 Bernd Schmidt <bernds@codesourcery.com>
* config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case.
* arm-modes.def (CC_NOTB): Don't define.
* config/arm/arm.md (arm_adddi3): Generate canonical RTL.
(adddi_sesidi_di, adddi_zesidi_di): Likewise.
(LTUGEU): New code_iterator.
(cnb, optab): New corresponding code_attrs.
(addsi3_carryin_<optab>): Renamed from addsi3_carryin. Change pattern
to canonical form. Operands 1 and 2 are commutative. Parametrize
using LTUGEU.
(addsi3_carryin_shift_<optab>): Likewise.
(addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2.
Operands 1 and 2 are commutative. Parametrize using LTUGEU.
(addsi3_carryin_alt1, addsi3_carryin_alt3): Remove.
(subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to
CC.
(arm_subsi3_insn): Allow constants for operand 0.
(compare_scc peephole for eq case): New.
(compare_scc splitters): Change CC_NOTB to CC.
2010-07-05 Richard Guenther <rguenther@suse.de> 2010-07-05 Richard Guenther <rguenther@suse.de>
* tree-ssa-loop-im.c (for_each_index): Do not handle * tree-ssa-loop-im.c (for_each_index): Do not handle
......
gcc/config/arm/arm-modes.def
...@@ -36,8 +36,6 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) ...@@ -36,8 +36,6 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
CC_Zmode should be used if only the Z flag is set correctly CC_Zmode should be used if only the Z flag is set correctly
CC_Cmode should be used if only the C flag is set correctly, after an CC_Cmode should be used if only the C flag is set correctly, after an
addition. addition.
CC_NOTBmode should be used if only the C flag is set as a not-borrow
flag, after a subtraction.
CC_Nmode should be used if only the N (sign) flag is set correctly CC_Nmode should be used if only the N (sign) flag is set correctly
CC_CZmode should be used if only the C and Z flags are correct CC_CZmode should be used if only the C and Z flags are correct
(used for DImode unsigned comparisons). (used for DImode unsigned comparisons).
...@@ -63,7 +61,6 @@ CC_MODE (CC_DLTU); ...@@ -63,7 +61,6 @@ CC_MODE (CC_DLTU);
CC_MODE (CC_DGEU); CC_MODE (CC_DGEU);
CC_MODE (CC_DGTU); CC_MODE (CC_DGTU);
CC_MODE (CC_C); CC_MODE (CC_C);
CC_MODE (CC_NOTB);
CC_MODE (CC_N); CC_MODE (CC_N);
/* Vector modes. */ /* Vector modes. */
......
gcc/config/arm/arm.c
...@@ -16341,14 +16341,6 @@ get_arm_condition_code (rtx comparison) ...@@ -16341,14 +16341,6 @@ get_arm_condition_code (rtx comparison)
default: gcc_unreachable (); default: gcc_unreachable ();
} }
case CC_NOTBmode:
switch (comp_code)
{
case LTU: return ARM_CC;
case GEU: return ARM_CS;
default: gcc_unreachable ();
}
case CC_CZmode: case CC_CZmode:
switch (comp_code) switch (comp_code)
{ {
......
gcc/config/arm/arm.md
...@@ -503,8 +503,8 @@ ...@@ -503,8 +503,8 @@
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
(plus:SI (match_dup 4) (match_dup 5))))] (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
" "
{ {
operands[3] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[0]);
...@@ -531,10 +531,10 @@ ...@@ -531,10 +531,10 @@
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
(plus:SI (ashiftrt:SI (match_dup 2)
(const_int 31)) (const_int 31))
(match_dup 4))))] (match_dup 4))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
" "
{ {
operands[3] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[0]);
...@@ -560,8 +560,8 @@ ...@@ -560,8 +560,8 @@
(compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
(plus:SI (match_dup 4) (const_int 0))))] (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
" "
{ {
operands[3] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[0]);
...@@ -849,60 +849,44 @@ ...@@ -849,60 +849,44 @@
[(set_attr "conds" "set")] [(set_attr "conds" "set")]
) )
(define_insn "*addsi3_carryin" (define_code_iterator LTUGEU [ltu geu])
[(set (match_operand:SI 0 "s_register_operand" "=r") (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (define_code_attr optab [(ltu "ltu") (geu "geu")])
(plus:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI"))))]
"TARGET_32BIT"
"adc%?\\t%0, %1, %2"
[(set_attr "conds" "use")]
)
(define_insn "*addsi3_carryin_shift"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "reg_or_int_operand" "rM")])
(match_operand:SI 1 "s_register_operand" "r"))))]
"TARGET_32BIT"
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
)
(define_insn "*addsi3_carryin_alt1" (define_insn "*addsi3_carryin_<optab>"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
(match_operand:SI 2 "arm_rhs_operand" "rI")) (match_operand:SI 2 "arm_rhs_operand" "rI"))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
"TARGET_32BIT" "TARGET_32BIT"
"adc%?\\t%0, %1, %2" "adc%?\\t%0, %1, %2"
[(set_attr "conds" "use")] [(set_attr "conds" "use")]
) )
(define_insn "*addsi3_carryin_alt2" (define_insn "*addsi3_carryin_alt2_<optab>"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
(match_operand:SI 1 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "%r"))
(match_operand:SI 2 "arm_rhs_operand" "rI")))] (match_operand:SI 2 "arm_rhs_operand" "rI")))]
"TARGET_32BIT" "TARGET_32BIT"
"adc%?\\t%0, %1, %2" "adc%?\\t%0, %1, %2"
[(set_attr "conds" "use")] [(set_attr "conds" "use")]
) )
(define_insn "*addsi3_carryin_alt3" (define_insn "*addsi3_carryin_shift_<optab>"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (plus:SI (plus:SI
(match_operand:SI 2 "arm_rhs_operand" "rI")) (match_operator:SI 2 "shift_operator"
(match_operand:SI 1 "s_register_operand" "r")))] [(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "reg_or_int_operand" "rM")])
(match_operand:SI 1 "s_register_operand" "r"))
(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
"TARGET_32BIT" "TARGET_32BIT"
"adc%?\\t%0, %1, %2" "adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")] [(set_attr "conds" "use")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
) )
(define_expand "incscc" (define_expand "incscc"
...@@ -1104,24 +1088,27 @@ ...@@ -1104,24 +1088,27 @@
; ??? Check Thumb-2 split length ; ??? Check Thumb-2 split length
(define_insn_and_split "*arm_subsi3_insn" (define_insn_and_split "*arm_subsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,rk,r") [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r")
(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n") (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r")
(match_operand:SI 2 "s_register_operand" "r, r, r")))] (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
rsb%?\\t%0, %2, %1 rsb%?\\t%0, %2, %1
sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2
sub%?\\t%0, %1, %2
#
#" #"
"TARGET_32BIT "&& ((GET_CODE (operands[1]) == CONST_INT
&& GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1])))
&& !const_ok_for_arm (INTVAL (operands[1]))" || (GET_CODE (operands[2]) == CONST_INT
&& !const_ok_for_arm (INTVAL (operands[2]))))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
" "
arm_split_constant (MINUS, SImode, curr_insn, arm_split_constant (MINUS, SImode, curr_insn,
INTVAL (operands[1]), operands[0], operands[2], 0); INTVAL (operands[1]), operands[0], operands[2], 0);
DONE; DONE;
" "
[(set_attr "length" "4,4,16") [(set_attr "length" "4,4,4,16,16")
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
...@@ -1153,10 +1140,10 @@ ...@@ -1153,10 +1140,10 @@
[(set_attr "conds" "set")] [(set_attr "conds" "set")]
) )
(define_insn "*subsi3_compare0_c" (define_insn "*subsi3_compare"
[(set (reg:CC_NOTB CC_REGNUM) [(set (reg:CC CC_REGNUM)
(compare:CC_NOTB (match_operand:SI 1 "arm_rhs_operand" "r,I") (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I")
(match_operand:SI 2 "arm_rhs_operand" "rI,r"))) (match_operand:SI 2 "arm_rhs_operand" "rI,r")))
(set (match_operand:SI 0 "s_register_operand" "=r,r") (set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"TARGET_32BIT" "TARGET_32BIT"
...@@ -9306,11 +9293,11 @@ ...@@ -9306,11 +9293,11 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && reload_completed" "TARGET_32BIT && reload_completed"
[(parallel [(parallel
[(set (reg:CC_NOTB CC_REGNUM) [(set (reg:CC CC_REGNUM)
(compare:CC_NOTB (const_int 1) (match_dup 1))) (compare:CC (const_int 1) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(minus:SI (const_int 1) (match_dup 1)))]) (minus:SI (const_int 1) (match_dup 1)))])
(cond_exec (ltu:CC_NOTB (reg:CC_NOTB CC_REGNUM) (const_int 0)) (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 0)))]) (set (match_dup 0) (const_int 0)))])
(define_split (define_split
...@@ -9362,7 +9349,7 @@ ...@@ -9362,7 +9349,7 @@
enum rtx_code rc = GET_CODE (operands[1]); enum rtx_code rc = GET_CODE (operands[1]);
tmp1 = gen_rtx_REG (mode, CC_REGNUM); tmp1 = gen_rtx_REG (mode, CC_REGNUM);
operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
if (mode == CCFPmode || mode == CCFPEmode) if (mode == CCFPmode || mode == CCFPEmode)
rc = reverse_condition_maybe_unordered (rc); rc = reverse_condition_maybe_unordered (rc);
...@@ -9371,6 +9358,27 @@ ...@@ -9371,6 +9358,27 @@
operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
}) })
;; Attempt to improve the sequence generated by the compare_scc splitters
;; not to use conditional execution.
(define_peephole2
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "arm_rhs_operand" "")))
(cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
(set (match_operand:SI 0 "register_operand" "") (const_int 0)))
(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))
(match_scratch:SI 3 "r")]
"TARGET_32BIT"
[(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
(parallel
[(set (reg:CC CC_REGNUM)
(compare:CC (const_int 0) (match_dup 3)))
(set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
(set (match_dup 0)
(plus:SI (plus:SI (match_dup 0) (match_dup 3))
(geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
(define_insn "*cond_move" (define_insn "*cond_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r") [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI (match_operator 3 "equality_operator" (if_then_else:SI (match_operator 3 "equality_operator"
......
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