Commit 7e964f49 by Vladimir Makarov Committed by Vladimir Makarov

re PR rtl-optimization/78671 (ICE: in extract_constrain_insn, at recog.c:2213…

re PR rtl-optimization/78671 (ICE: in extract_constrain_insn, at recog.c:2213 with -Og -march=skylake-avx512)

2016-12-08  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/78671
	* lra-assign.c (lra-assigns.c): Check prohibited regs for an
	allocno class.

2016-12-08  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/78671
	* gcc.target/i386/pr78671.c: New.

From-SVN: r243462
parent 060162e0
2016-12-08 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/78671
* lra-assign.c (lra-assigns.c): Check prohibited regs for an
allocno class.
2016-12-08 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/i386.h (HARD_REGNO_NREGS): Use GENERAL_REGNO_P.
......@@ -628,9 +628,13 @@ find_hard_regno_for_1 (int regno, int *cost, int try_only_hard_regno,
hard_regno = ira_class_hard_regs[rclass][i];
if (! overlaps_hard_reg_set_p (conflict_set,
PSEUDO_REGNO_MODE (regno), hard_regno)
/* We can not use prohibited_class_mode_regs because it is
not defined for all classes. */
&& HARD_REGNO_MODE_OK (hard_regno, PSEUDO_REGNO_MODE (regno))
/* We can not use prohibited_class_mode_regs for all classes
because it is not defined for all classes. */
&& (ira_allocno_class_translate[rclass] != rclass
|| ! TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[rclass][PSEUDO_REGNO_MODE (regno)],
hard_regno))
&& ! TEST_HARD_REG_BIT (impossible_start_hard_regs, hard_regno)
&& (nregs_diff == 0
|| (WORDS_BIG_ENDIAN
......
2016-12-08 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/78671
* gcc.target/i386/pr78671.c: New.
2015-12-08 Wilco Dijkstra <wdijkstr@arm.com>
PR target/78733
......
/* { dg-do compile } */
/* { dg-options "-march=skylake-avx512 -Og" } */
typedef unsigned __int128 u128;
typedef unsigned __int128 v64u128 __attribute__ ((vector_size (64)));
v64u128
foo (u128 u128_3, v64u128 v64u128_3, v64u128 v64u128_2, v64u128 v64u128_1,
v64u128 v64u128_0)
{
v64u128_0 <<= 1;
v64u128_2 >>= 0 != v64u128_2;
v64u128_3[v64u128_3[0]] &= 1;
v64u128_3 = v64u128_3 & 1;
v64u128_2 = v64u128_2 >> 1 | v64u128_2 << v64u128_1[0];
v64u128_0[0] >>= 127;
return u128_3 + v64u128_0 + v64u128_2 + v64u128_3;
}
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