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riscv-gcc-1
Commit 7dac2f89 by Eric Christopher
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[multiple changes] 

2001-07-05  Eric Christopher  <echristo@redhat.com>

        * config/mips/mips.h (MASK_MIPS3900): Remove.
        (MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
        MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
        (TARGET_MIPS3900): Change to use mips_arch.
        (TARGET_MIPS4000): New.
        (TARGET_MIPS4100): New.
        (TARGET_MIPS4300): New.
        (TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
        (SUBTARGET_TARGET_OPTIONS): Add -march. Change help text
        for -mipsX.
        (GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
        (ISA_HAS_BRANCHLIKELY): To here.
        (CC1_CPU_SPEC):  New.
        (CC1_SPEC): Use here.  Remove 4650 and 3900 options.
        (mips_arch_string): Declare.
        (mips_arch): Declare.
        (TARGET_OPTIONS): Add -march and -mtune.

        * config/mips/mips.c (mips_arch_string): New.
        (mips_arch): New.
        (override_options): Handle -march for codegen and -mtune
        for scheduling. Use mips_arch. Move tx39 target default here.
        (mips_parse_cpu): Move error message to override_options.

        * config/mips/r3900.h (TARGET_DEFAULT): Remove.

        * config/mips/mips.md: Use TARGET_MIPS4000 and TARGET_MIPS4300.

        * doc/invoke.texi (Option Summary): Add -march and -mtune entries.
        (MIPS Options): Ditto.  Change mcpu entry to historical text.

2001-07-05  H.J. Lu  (hjl@gnu.org)

        * config/mips/mips.c (mips_parse_cpu): New function to parse
        -march=*/-mcpu=*.

From-SVN: r43803
parent 8a749647
Showing with 600 additions and 440 deletions
gcc/ChangeLog
2001-07-05 Eric Christopher <echristo@redhat.com>
* config/mips/mips.h (MASK_MIPS3900): Remove.
(MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
(TARGET_MIPS3900): Change to use mips_arch.
(TARGET_MIPS4000): New.
(TARGET_MIPS4100): New.
(TARGET_MIPS4300): New.
(TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
(SUBTARGET_TARGET_OPTIONS): Add -march. Change help text
for -mipsX.
(GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
(ISA_HAS_BRANCHLIKELY): To here.
(CC1_CPU_SPEC): New.
(CC1_SPEC): Use here. Remove 4650 and 3900 options.
(mips_arch_string): Declare.
(mips_arch): Declare.
(TARGET_OPTIONS): Add -march and -mtune.
* config/mips/mips.c (mips_arch_string): New.
(mips_arch): New.
(override_options): Handle -march for codegen and -mtune
for scheduling. Use mips_arch. Move tx39 target default here.
(mips_parse_cpu): Move error message to override_options.
* config/mips/r3900.h (TARGET_DEFAULT): Remove.
* config/mips/mips.md: Use TARGET_MIPS4000 and TARGET_MIPS4300.
* doc/invoke.texi (Option Summary): Add -march and -mtune entries.
(MIPS Options): Ditto. Change mcpu entry to historical text.
2001-07-05 H.J. Lu (hjl@gnu.org)
* config/mips/mips.c (mips_parse_cpu): New function to parse
-march=*/-mcpu=*.
2001-07-05 Jim Wilson <wilson@redhat.com>
* config/ia64/lib1funcs.asm: Revert 2001-07-02 change.
......@@ -10,8 +48,8 @@
2001-07-04 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/m68hc11.md ("*ashlsi3"): Operand 1 can be a memory
reference using the stack pointer, adjust it since we push Y
* config/m68hc11/m68hc11.md ("*ashlsi3"): Operand 1 can be a memory
reference using the stack pointer, adjust it since we push Y
temporarily.
("*ashrsi3"): Likewise.
("*lshrsi3"): Likewise.
......
gcc/config/mips/mips.c
......@@ -86,7 +86,7 @@ static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
enum machine_mode));
static int m16_check_op PARAMS ((rtx, int, int, int));
static void block_move_loop PARAMS ((rtx, rtx,
unsigned int,
unsigned int,
int,
rtx, rtx));
static void block_move_call PARAMS ((rtx, rtx, rtx));
......@@ -107,6 +107,7 @@ static void abort_with_insn PARAMS ((rtx, const char *))
ATTRIBUTE_NORETURN;
static int symbolic_expression_p PARAMS ((rtx));
static void mips_add_gc_roots PARAMS ((void));
static enum processor_type mips_parse_cpu PARAMS ((const char *));
/* Global variables for machine-dependent things. */
......@@ -193,7 +194,13 @@ enum cmp_type branch_type;
static int prev_half_pic_ptrs = 0;
static int prev_half_pic_refs = 0;
/* which cpu are we scheduling for */
/* The target cpu for code generation. */
enum processor_type mips_arch;
/* The target cpu for optimization and scheduling. */
enum processor_type mips_tune;
/* Historical option for code generation and scheduling. */
enum processor_type mips_cpu;
/* which instruction set architecture to use. */
......@@ -207,6 +214,8 @@ int mips_abi;
/* Strings to hold which cpu and instruction set architecture to use. */
const char *mips_cpu_string; /* for -mcpu=<xxx> */
const char *mips_arch_string; /* for -march=<xxx> */
const char *mips_tune_string; /* for -mtune=<xxx> */
const char *mips_isa_string; /* for -mips{1,2,3,4} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
......@@ -219,7 +228,7 @@ int mips16;
just a way to avoid using up another bit in target_flags. */
const char *mips_no_mips16_string;
/* This is only used to determine if an type size setting option was
/* This is only used to determine if an type size setting option was
explicitly specified (-mlong64, -mint64, -mlong32). The specs
set this option if such an option is used. */
const char *mips_explicit_type_size_string;
......@@ -1220,7 +1229,7 @@ int
mips_check_split (address, mode)
rtx address;
enum machine_mode mode;
{
{
/* ??? This is the same check used in simple_memory_operand.
We use it here because LO_SUM is not offsettable. */
if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
......@@ -1244,7 +1253,7 @@ mips_reg_mode_ok_for_base_p (reg, mode, strict)
enum machine_mode mode;
int strict;
{
return (strict
return (strict
? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
: GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
}
......@@ -1260,111 +1269,111 @@ mips_legitimate_address_p (mode, xinsn, strict)
rtx xinsn;
int strict;
{
if (TARGET_DEBUG_B_MODE)
{
GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
strict ? "" : "not ");
GO_DEBUG_RTX (xinsn);
}
/* Check for constant before stripping off SUBREG, so that we don't
accept (subreg (const_int)) which will fail to reload. */
if (CONSTANT_ADDRESS_P (xinsn)
if (TARGET_DEBUG_B_MODE)
{
GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
strict ? "" : "not ");
GO_DEBUG_RTX (xinsn);
}
/* Check for constant before stripping off SUBREG, so that we don't
accept (subreg (const_int)) which will fail to reload. */
if (CONSTANT_ADDRESS_P (xinsn)
&& ! (mips_split_addresses && mips_check_split (xinsn, mode))
&& (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
return 1;
while (GET_CODE (xinsn) == SUBREG)
xinsn = SUBREG_REG (xinsn);
/* The mips16 can only use the stack pointer as a base register when
loading SImode or DImode values. */
if (GET_CODE (xinsn) == REG
&& mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
return 1;
if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
{
register rtx xlow0 = XEXP (xinsn, 0);
register rtx xlow1 = XEXP (xinsn, 1);
while (GET_CODE (xlow0) == SUBREG)
xlow0 = SUBREG_REG (xlow0);
if (GET_CODE (xlow0) == REG
&& (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
return 1;
while (GET_CODE (xinsn) == SUBREG)
xinsn = SUBREG_REG (xinsn);
/* The mips16 can only use the stack pointer as a base register when
loading SImode or DImode values. */
if (GET_CODE (xinsn) == REG
&& mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
return 1;
if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
{
register rtx xlow0 = XEXP (xinsn, 0);
register rtx xlow1 = XEXP (xinsn, 1);
while (GET_CODE (xlow0) == SUBREG)
xlow0 = SUBREG_REG (xlow0);
if (GET_CODE (xlow0) == REG
&& mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
&& mips_check_split (xlow1, mode))
return 1;
}
if (GET_CODE (xinsn) == PLUS)
{
register rtx xplus0 = XEXP (xinsn, 0);
register rtx xplus1 = XEXP (xinsn, 1);
register enum rtx_code code0;
register enum rtx_code code1;
while (GET_CODE (xplus0) == SUBREG)
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
while (GET_CODE (xplus1) == SUBREG)
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
/* The mips16 can only use the stack pointer as a base register
when loading SImode or DImode values. */
if (code0 == REG
&& mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
{
return 1;
}
if (GET_CODE (xinsn) == PLUS)
{
register rtx xplus0 = XEXP (xinsn, 0);
register rtx xplus1 = XEXP (xinsn, 1);
register enum rtx_code code0;
register enum rtx_code code1;
while (GET_CODE (xplus0) == SUBREG)
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
while (GET_CODE (xplus1) == SUBREG)
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
/* The mips16 can only use the stack pointer as a base register
when loading SImode or DImode values. */
if (code0 == REG
&& mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
{
if (code1 == CONST_INT && SMALL_INT (xplus1))
return 1;
/* On the mips16, we represent GP relative offsets in RTL.
These are 16 bit signed values, and can serve as register
offsets. */
if (TARGET_MIPS16
&& mips16_gp_offset_p (xplus1))
return 1;
/* For some code sequences, you actually get better code by
pretending that the MIPS supports an address mode of a
constant address + a register, even though the real
machine doesn't support it. This is because the
assembler can use $r1 to load just the high 16 bits, add
in the register, and fold the low 16 bits into the memory
reference, whereas the compiler generates a 4 instruction
sequence. On the other hand, CSE is not as effective.
It would be a win to generate the lui directly, but the
MIPS assembler does not have syntax to generate the
appropriate relocation. */
/* Also accept CONST_INT addresses here, so no else. */
/* Reject combining an embedded PIC text segment reference
with a register. That requires an additional
instruction. */
/* ??? Reject combining an address with a register for the MIPS
64 bit ABI, because the SGI assembler can not handle this. */
if (!TARGET_DEBUG_A_MODE
&& (mips_abi == ABI_32
|| mips_abi == ABI_O64
|| mips_abi == ABI_EABI)
&& CONSTANT_ADDRESS_P (xplus1)
&& ! mips_split_addresses
&& (!TARGET_EMBEDDED_PIC
|| code1 != CONST
|| GET_CODE (XEXP (xplus1, 0)) != MINUS)
/* When assembling for machines with 64 bit registers,
/* On the mips16, we represent GP relative offsets in RTL.
These are 16 bit signed values, and can serve as register
offsets. */
if (TARGET_MIPS16
&& mips16_gp_offset_p (xplus1))
return 1;
/* For some code sequences, you actually get better code by
pretending that the MIPS supports an address mode of a
constant address + a register, even though the real
machine doesn't support it. This is because the
assembler can use $r1 to load just the high 16 bits, add
in the register, and fold the low 16 bits into the memory
reference, whereas the compiler generates a 4 instruction
sequence. On the other hand, CSE is not as effective.
It would be a win to generate the lui directly, but the
MIPS assembler does not have syntax to generate the
appropriate relocation. */
/* Also accept CONST_INT addresses here, so no else. */
/* Reject combining an embedded PIC text segment reference
with a register. That requires an additional
instruction. */
/* ??? Reject combining an address with a register for the MIPS
64 bit ABI, because the SGI assembler can not handle this. */
if (!TARGET_DEBUG_A_MODE
&& (mips_abi == ABI_32
|| mips_abi == ABI_O64
|| mips_abi == ABI_EABI)
&& CONSTANT_ADDRESS_P (xplus1)
&& ! mips_split_addresses
&& (!TARGET_EMBEDDED_PIC
|| code1 != CONST
|| GET_CODE (XEXP (xplus1, 0)) != MINUS)
/* When assembling for machines with 64 bit registers,
the assembler will not sign-extend the constant "foo"
in "la x, foo(x)" */
&& (!TARGET_64BIT || (INTVAL (xplus1) > 0))
&& !TARGET_MIPS16)
return 1;
}
}
if (TARGET_DEBUG_B_MODE)
&& !TARGET_MIPS16)
return 1;
}
}
if (TARGET_DEBUG_B_MODE)
GO_PRINTF ("Not a legitimate address\n");
/* The address was not legitimate. */
return 0;
}
......@@ -1793,7 +1802,7 @@ embedded_pic_offset (x)
rtx seq;
embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
/* Output code at function start to initialize the pseudo-reg. */
/* ??? We used to do this in FINALIZE_PIC, but that does not work for
inline functions, because it is called after RTL for the function
......@@ -2199,7 +2208,7 @@ mips_move_1word (operands, insn, unsignedp)
if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
abort ();
sprintf (volatile_buffer, "%%{%s%%}", ret);
ret = volatile_buffer;
}
......@@ -2259,7 +2268,7 @@ mips_move_2words (operands, insn)
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
}
/* Sanity check. */
if (GET_CODE (operands[1]) == SIGN_EXTEND
&& code1 != REG
......@@ -2392,7 +2401,7 @@ mips_move_2words (operands, insn)
or higher. For !TARGET_64BIT && gp registers we
need to avoid this by using two li instructions
instead. */
if (ISA_HAS_64BIT_REGS
if (ISA_HAS_64BIT_REGS
&& ! TARGET_64BIT
&& ! FP_REG_P (regno0))
{
......@@ -2460,7 +2469,7 @@ mips_move_2words (operands, insn)
: "mt%0\t%.\n");
}
}
else if (code1 == CONST_INT && GET_MODE (op0) == DImode
&& GP_REG_P (regno0))
{
......@@ -2661,7 +2670,7 @@ mips_move_2words (operands, insn)
if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
abort ();
sprintf (volatile_buffer, "%%{%s%%}", ret);
ret = volatile_buffer;
}
......@@ -2748,7 +2757,7 @@ mips_address_cost (addr)
return 4;
}
/* Return nonzero if X is an address which needs a temporary register when
/* Return nonzero if X is an address which needs a temporary register when
reloaded while generating PIC code. */
int
......@@ -3059,7 +3068,7 @@ gen_conditional_branch (operands, test_code)
emit_insn (gen_rtx_SET (VOIDmode, reg,
gen_rtx (test_code == NE ? EQ : test_code,
CCmode, cmp0, cmp1)));
test_code = test_code == NE ? EQ : NE;
mode = CCmode;
cmp0 = reg;
......@@ -3156,7 +3165,7 @@ gen_conditional_move (operands)
}
else if (cmp_code == NE)
cmp_code = EQ, move_code = EQ;
if (mode == SImode || mode == DImode)
cmp_mode = mode;
else if (mode == SFmode || mode == DFmode)
......@@ -3381,7 +3390,7 @@ expand_block_move (operands)
else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
&& align == (unsigned) UNITS_PER_WORD)
move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
dest_reg),
......@@ -3445,7 +3454,7 @@ expand_block_move (operands)
block_move_call (dest_reg, src_reg, bytes_rtx);
}
/* Emit load/stores for a small constant block_move.
/* Emit load/stores for a small constant block_move.
operands[0] is the memory address of the destination.
operands[1] is the memory address of the source.
......@@ -3945,7 +3954,7 @@ function_arg (cum, mode, type, named)
fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
fprintf (stderr, ", %d ) = ", named);
}
cum->last_arg_fp = 0;
switch (mode)
......@@ -4108,8 +4117,8 @@ function_arg (cum, mode, type, named)
regno + FP_ARG_FIRST - GP_ARG_FIRST);
else
reg = gen_rtx_REG (word_mode, regno);
XVECEXP (ret, 0, i)
XVECEXP (ret, 0, i)
= gen_rtx_EXPR_LIST (VOIDmode, reg,
GEN_INT (bitpos / BITS_PER_UNIT));
......@@ -4219,15 +4228,15 @@ function_arg_partial_nregs (cum, mode, type, named)
/* Create the va_list data type.
We keep 3 pointers, and two offsets.
Two pointers are to the overflow area, which starts at the CFA.
Two pointers are to the overflow area, which starts at the CFA.
One of these is constant, for addressing into the GPR save area below it.
The other is advanced up the stack through the overflow region.
The third pointer is to the GPR save area. Since the FPR save area
is just below it, we can address FPR slots off this pointer.
We also keep two one-byte offsets, which are to be subtracted from the
constant pointers to yield addresses in the GPR and FPR save areas.
These are downcounted as float or non-float arguments are used,
and when they get to zero, the argument must be obtained from the
These are downcounted as float or non-float arguments are used,
and when they get to zero, the argument must be obtained from the
overflow region.
If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
and a single pointer is enough. It's started at the GPR save area,
......@@ -4307,8 +4316,8 @@ mips_va_start (stdarg_p, valist, nextarg)
if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
{
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, gtop, ftop, goff, foff;
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, gtop, ftop, goff, foff;
tree gprv;
int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
int fpr_save_offset;
......@@ -4347,7 +4356,7 @@ mips_va_start (stdarg_p, valist, nextarg)
8 byte boundary. This means that the above calculation should
take into account the exact sequence of floats and non-floats
which make up the excess. That calculation should be rolled
into the code which sets the current_function_args_info struct.
into the code which sets the current_function_args_info struct.
The above then reduces to a fetch from that struct. */
......@@ -4377,7 +4386,7 @@ mips_va_start (stdarg_p, valist, nextarg)
fpr_save_offset += 4;
}
if (fpr_save_offset)
gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
build_int_2 (-fpr_save_offset,-1));
t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
......@@ -4459,8 +4468,8 @@ mips_va_arg (valist, type)
{
int indirect;
rtx r, lab_over = NULL_RTX, lab_false;
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, gtop, ftop, goff, foff;
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, gtop, ftop, goff, foff;
indirect
= function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
......@@ -4484,13 +4493,13 @@ mips_va_arg (valist, type)
{
t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
build_int_2 (2*UNITS_PER_WORD - 1, 0));
t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
build_int_2 (-2*UNITS_PER_WORD, -1));
t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
size_int (rsize));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
......@@ -4545,7 +4554,7 @@ mips_va_arg (valist, type)
if (r != addr_rtx)
emit_move_insn (addr_rtx, r);
/* Emit code for foff-=8.
/* Emit code for foff-=8.
Advances the offset up FPR save area by one double */
t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
......@@ -4555,8 +4564,8 @@ mips_va_arg (valist, type)
emit_jump (lab_over);
emit_barrier ();
emit_label (lab_false);
if (!TARGET_64BIT)
if (!TARGET_64BIT)
{
/* For mips2, the overflow area contains mixed size items.
If a 4-byte int is followed by an 8-byte float, then
......@@ -4571,7 +4580,7 @@ mips_va_arg (valist, type)
/* Emit code for addr_rtx = the ovfl pointer into overflow area.
Regardless of mips2, postincrement the ovfl pointer by 8. */
t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
size_int (8));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
......@@ -4590,7 +4599,7 @@ mips_va_arg (valist, type)
&& TREE_CODE (type) == INTEGER_TYPE
&& TYPE_PRECISION (type) == 64)
{
/* In mips2, int takes 32 bits of the GPR save area, but
/* In mips2, int takes 32 bits of the GPR save area, but
longlong takes an aligned 64 bits. So, emit code
to zero the low order bits of goff, thus aligning
the later calculation of (gtop-goff) upwards. */
......@@ -4620,7 +4629,7 @@ mips_va_arg (valist, type)
/* Emit code for goff = goff - step_size.
Advances the offset up GPR save area over the item. */
t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
build_int_2 (step_size, 0));
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
......@@ -4629,9 +4638,9 @@ mips_va_arg (valist, type)
emit_jump (lab_over);
emit_barrier ();
emit_label (lab_false);
/* Emit code for addr_rtx -> overflow area, postinc by step_size */
t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
size_int (step_size));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
......@@ -4659,7 +4668,7 @@ mips_va_arg (valist, type)
/* Not EABI. */
int align;
/* ??? The original va-mips.h did always align, despite the fact
/* ??? The original va-mips.h did always align, despite the fact
that alignments <= UNITS_PER_WORD are preserved by the va_arg
increment mechanism. */
......@@ -4669,7 +4678,7 @@ mips_va_arg (valist, type)
align = 8;
else
align = 4;
t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
build_int_2 (align - 1, 0));
t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
......@@ -4712,7 +4721,7 @@ override_options ()
/* If both single-float and soft-float are set, then clear the one that
was set by TARGET_DEFAULT, leaving the one that was set by the
user. We assume here that the specs prevent both being set by the
user. We assume here that the specs prevent both being set by the
user. */
#ifdef TARGET_DEFAULT
if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
......@@ -4773,7 +4782,7 @@ override_options ()
error ("bad value (%s) for -mabi= switch", mips_abi_string);
/* A specified ISA defaults the ABI if it was not specified. */
if (mips_abi_string == 0 && mips_isa_string
if (mips_abi_string == 0 && mips_isa_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
if (! ISA_HAS_64BIT_REGS)
......@@ -4783,7 +4792,7 @@ override_options ()
}
/* A specified ABI defaults the ISA if it was not specified. */
else if (mips_isa_string == 0 && mips_abi_string
else if (mips_isa_string == 0 && mips_abi_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
if (mips_abi == ABI_32)
......@@ -4829,133 +4838,111 @@ override_options ()
greater than that supported by the default processor, then the user gets
an error. Normally, the compiler will just default to the base level cpu
for the indicated isa. */
if (mips_cpu_string == 0)
mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
if (mips_arch_string == 0)
mips_arch_string = MIPS_CPU_STRING_DEFAULT;
if (mips_tune_string == 0)
mips_tune_string = MIPS_CPU_STRING_DEFAULT;
#endif
/* Identify the processor type. */
if (mips_cpu_string == 0
|| ! strcmp (mips_cpu_string, "default")
|| ! strcmp (mips_cpu_string, "DEFAULT"))
if (mips_cpu_string != 0)
{
mips_cpu = mips_parse_cpu (mips_cpu_string);
if (mips_cpu == PROCESSOR_DEFAULT)
{
error ("bad value (%s) for -mcpu= switch", mips_arch_string);
mips_cpu_string = "default";
}
mips_arch = mips_cpu;
mips_tune = mips_cpu;
}
if (mips_arch_string == 0
|| ! strcmp (mips_arch_string, "default")
|| ! strcmp (mips_arch_string, "DEFAULT"))
{
switch (mips_isa)
{
default:
mips_cpu_string = "3000";
mips_cpu = PROCESSOR_R3000;
mips_arch_string = "3000";
mips_arch = PROCESSOR_R3000;
break;
case 2:
mips_cpu_string = "6000";
mips_cpu = PROCESSOR_R6000;
mips_arch_string = "6000";
mips_arch = PROCESSOR_R6000;
break;
case 3:
mips_cpu_string = "4000";
mips_cpu = PROCESSOR_R4000;
mips_arch_string = "4000";
mips_arch = PROCESSOR_R4000;
break;
case 4:
mips_cpu_string = "8000";
mips_cpu = PROCESSOR_R8000;
mips_arch_string = "8000";
mips_arch = PROCESSOR_R8000;
break;
}
}
else
{
const char *p = mips_cpu_string;
int seen_v = 0;
/* We need to cope with the various "vr" prefixes for the NEC 4300
and 4100 processors. */
if (*p == 'v' || *p == 'V')
seen_v = 1, p++;
if (*p == 'r' || *p == 'R')
p++;
/* Since there is no difference between a R2000 and R3000 in
terms of the scheduler, we collapse them into just an R3000. */
mips_cpu = PROCESSOR_DEFAULT;
switch (*p)
mips_arch = mips_parse_cpu (mips_arch_string);
if (mips_arch == PROCESSOR_DEFAULT)
{
case '2':
if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
mips_cpu = PROCESSOR_R3000;
break;
case '3':
if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
mips_cpu = PROCESSOR_R3000;
else if (!strcmp (p, "3900"))
mips_cpu = PROCESSOR_R3900;
break;
case '4':
if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
mips_cpu = PROCESSOR_R4000;
/* The vr4100 is a non-FP ISA III processor with some extra
instructions. */
else if (!strcmp (p, "4100"))
{
mips_cpu = PROCESSOR_R4100;
target_flags |= MASK_SOFT_FLOAT ;
}
/* The vr4300 is a standard ISA III processor, but with a different
pipeline. */
else if (!strcmp (p, "4300"))
mips_cpu = PROCESSOR_R4300;
/* The r4400 is exactly the same as the r4000 from the compiler's
viewpoint. */
else if (!strcmp (p, "4400"))
mips_cpu = PROCESSOR_R4000;
else if (!strcmp (p, "4600"))
mips_cpu = PROCESSOR_R4600;
else if (!strcmp (p, "4650"))
mips_cpu = PROCESSOR_R4650;
break;
case '5':
if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
mips_cpu = PROCESSOR_R5000;
error ("bad value (%s) for -march= switch", mips_arch_string);
mips_arch_string = "default";
}
}
if (mips_tune_string == 0
|| ! strcmp (mips_tune_string, "default")
|| ! strcmp (mips_tune_string, "DEFAULT"))
{
if (mips_arch != PROCESSOR_DEFAULT)
mips_tune == mips_arch;
else
switch (mips_isa)
{
default:
mips_tune_string = "3000";
mips_tune = PROCESSOR_R3000;
break;
case '6':
if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
mips_cpu = PROCESSOR_R6000;
case 2:
mips_tune_string = "6000";
mips_tune = PROCESSOR_R6000;
break;
case '8':
if (!strcmp (p, "8000"))
mips_cpu = PROCESSOR_R8000;
case 3:
mips_tune_string = "4000";
mips_tune = PROCESSOR_R4000;
break;
case 'o':
if (!strcmp (p, "orion"))
mips_cpu = PROCESSOR_R4600;
case 4:
mips_tune_string = "8000";
mips_tune = PROCESSOR_R8000;
break;
}
if (seen_v
&& mips_cpu != PROCESSOR_R4300
&& mips_cpu != PROCESSOR_R4100
&& mips_cpu != PROCESSOR_R5000)
mips_cpu = PROCESSOR_DEFAULT;
if (mips_cpu == PROCESSOR_DEFAULT)
}
else
{
mips_tune = mips_parse_cpu (mips_tune_string);
if (mips_tune == PROCESSOR_DEFAULT)
{
error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
mips_cpu_string = "default";
error ("bad value (%s) for -mtune= switch", mips_tune_string);
mips_tune_string = "default";
}
}
if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
|| (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
|| mips_cpu == PROCESSOR_R4600
|| mips_cpu == PROCESSOR_R4650)
/* Handle processor configuration based on architecture. */
if (TARGET_MIPS4100 || TARGET_MIPS3900)
target_flags |= MASK_SOFT_FLOAT;
if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
|| (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
|| ((mips_arch == PROCESSOR_R4000
|| mips_arch == PROCESSOR_R4100
|| mips_arch == PROCESSOR_R4300
|| mips_arch == PROCESSOR_R4600
|| mips_arch == PROCESSOR_R4650)
&& mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
error ("-march=%s does not support -mips%d", mips_arch_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
if (! ISA_HAS_64BIT_REGS)
......@@ -5185,11 +5172,11 @@ override_options ()
/* Provide default values for align_* for 64-bit targets. */
if (TARGET_64BIT && !TARGET_MIPS16)
{
if (align_loops == 0)
if (align_loops == 0)
align_loops = 8;
if (align_jumps == 0)
if (align_jumps == 0)
align_jumps = 8;
if (align_functions == 0)
if (align_functions == 0)
align_functions = 8;
}
......@@ -5407,7 +5394,7 @@ print_operand (file, op, letter)
fputs (".set\tnoat\n\t", file);
break;
case ']':
case ']':
if (set_noat == 0)
error ("internal error: %%] found without a %%[ in assembler pattern");
else if (--set_noat == 0)
......@@ -5880,14 +5867,14 @@ mips_output_lineno (stream, line)
fprintf (stream, "\n\t%s.loc\t%d %d\n",
(ignore_line_number) ? "#" : "",
num_source_filenames, line);
LABEL_AFTER_LOC (stream);
}
}
/* Output an ASCII string, in a space-saving way. */
void
void
mips_output_ascii (stream, string_param, len)
FILE *stream;
const char *string_param;
......@@ -5898,70 +5885,70 @@ mips_output_ascii (stream, string_param, len)
register const unsigned char *string =
(const unsigned char *)string_param;
fprintf (stream, "\t.ascii\t\"");
for (i = 0; i < len; i++)
{
register int c = string[i];
switch (c)
{
case '\"':
case '\\':
putc ('\\', stream);
putc (c, stream);
cur_pos += 2;
break;
case TARGET_NEWLINE:
fputs ("\\n", stream);
if (i+1 < len
&& (((c = string[i+1]) >= '\040' && c <= '~')
|| c == TARGET_TAB))
cur_pos = 32767; /* break right here */
else
cur_pos += 2;
break;
case TARGET_TAB:
fputs ("\\t", stream);
cur_pos += 2;
break;
case TARGET_FF:
fputs ("\\f", stream);
cur_pos += 2;
break;
case TARGET_BS:
fputs ("\\b", stream);
cur_pos += 2;
break;
case TARGET_CR:
fputs ("\\r", stream);
cur_pos += 2;
break;
default:
if (c >= ' ' && c < 0177)
{
putc (c, stream);
cur_pos++;
}
else
{
fprintf (stream, "\\%03o", c);
cur_pos += 4;
}
}
if (cur_pos > 72 && i+1 < len)
{
cur_pos = 17;
fprintf (stream, "\"\n\t.ascii\t\"");
}
}
fprintf (stream, "\"\n");
fprintf (stream, "\t.ascii\t\"");
for (i = 0; i < len; i++)
{
register int c = string[i];
switch (c)
{
case '\"':
case '\\':
putc ('\\', stream);
putc (c, stream);
cur_pos += 2;
break;
case TARGET_NEWLINE:
fputs ("\\n", stream);
if (i+1 < len
&& (((c = string[i+1]) >= '\040' && c <= '~')
|| c == TARGET_TAB))
cur_pos = 32767; /* break right here */
else
cur_pos += 2;
break;
case TARGET_TAB:
fputs ("\\t", stream);
cur_pos += 2;
break;
case TARGET_FF:
fputs ("\\f", stream);
cur_pos += 2;
break;
case TARGET_BS:
fputs ("\\b", stream);
cur_pos += 2;
break;
case TARGET_CR:
fputs ("\\r", stream);
cur_pos += 2;
break;
default:
if (c >= ' ' && c < 0177)
{
putc (c, stream);
cur_pos++;
}
else
{
fprintf (stream, "\\%03o", c);
cur_pos += 4;
}
}
if (cur_pos > 72 && i+1 < len)
{
cur_pos = 17;
fprintf (stream, "\"\n\t.ascii\t\"");
}
}
fprintf (stream, "\"\n");
}
/* If defined, a C statement to be executed just prior to the output of
......@@ -6068,9 +6055,9 @@ mips_asm_file_start (stream)
asm_out_data_file = asm_out_text_file = stream;
if (flag_verbose_asm)
fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
ASM_COMMENT_START,
mips_section_threshold, mips_cpu_string, mips_isa);
mips_section_threshold, mips_arch_string, mips_isa);
}
/* If we are optimizing the global pointer, emit the text section now and any
......@@ -6117,7 +6104,7 @@ mips_asm_file_end (file)
}
}
}
if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
{
fprintf (file, "\n\t.text\n");
......@@ -6373,7 +6360,7 @@ compute_frame_size (size)
The gp reg is callee saved in the 64 bit ABI, so all routines must
save the gp reg. This is not a leaf routine if -p, because of the
call to mcount. */
if (total_size == extra_size
if (total_size == extra_size
&& (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
&& ! profile_flag)
total_size = extra_size = 0;
......@@ -6646,7 +6633,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
insn = emit_move_insn (mem_rtx, reg_rtx);
RTX_FRAME_RELATED_P (insn) = 1;
}
else if (!TARGET_ABICALLS
else if (!TARGET_ABICALLS
|| (mips_abi != ABI_32 && mips_abi != ABI_O64)
|| regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
{
......@@ -6660,7 +6647,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
}
else
{
if (store_p || !TARGET_ABICALLS
if (store_p || !TARGET_ABICALLS
|| (mips_abi != ABI_32 && mips_abi != ABI_O64)
|| regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
{
......@@ -6690,7 +6677,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
? (store_p) ? "sd" : "ld"
: (store_p) ? "sw" : "lw"),
reg_names[r]);
fprintf (file, HOST_WIDE_INT_PRINT_DEC,
fprintf (file, HOST_WIDE_INT_PRINT_DEC,
gp_offset - base_offset);
fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
if (! store_p
......@@ -7103,10 +7090,10 @@ mips_expand_prologue ()
/* For arguments passed in registers, find the register number
of the first argument in the variable part of the argument list,
otherwise GP_ARG_LAST+1. Note also if the last argument is
otherwise GP_ARG_LAST+1. Note also if the last argument is
the varargs special argument, and treat it as part of the
variable arguments.
This is only needed if store_args_on_stack is true. */
INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
......@@ -7602,7 +7589,7 @@ mips_expand_epilogue ()
g6_rtx));
tsize = 0;
}
if (tsize && tsize != orig_tsize)
tsize_rtx = GEN_INT (tsize);
}
......@@ -7705,7 +7692,7 @@ symbolic_expression_p (x)
if (GET_CODE (x) == CONST)
return symbolic_expression_p (XEXP (x, 0));
if (GET_RTX_CLASS (GET_CODE (x)) == '1')
return symbolic_expression_p (XEXP (x, 0));
......@@ -7742,7 +7729,7 @@ mips_select_rtx_section (mode, x)
{
/* For hosted applications, always put constants in small data if
possible, as this gives the best performance. */
if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
&& mips_section_threshold > 0)
SMALL_DATA_SECTION ();
......@@ -7863,8 +7850,8 @@ mips_function_value (valtype, func)
}
else if (TREE_CODE (valtype) == RECORD_TYPE
&& mips_abi != ABI_32
&& mips_abi != ABI_O64
&& mips_abi != ABI_32
&& mips_abi != ABI_O64
&& mips_abi != ABI_EABI)
{
/* A struct with only one or two floating point fields is returned in
......@@ -7883,7 +7870,7 @@ mips_function_value (valtype, func)
fields[i++] = field;
}
/* Must check i, so that we reject structures with no elements. */
if (! field)
{
......@@ -7954,8 +7941,8 @@ function_arg_pass_by_reference (cum, mode, type, named)
here hopefully is not relevant to mips_va_arg. */
if (cum && MUST_PASS_IN_STACK (mode, type))
{
/* Don't pass the actual CUM to FUNCTION_ARG, because we would
get double copies of any offsets generated for small structs
/* Don't pass the actual CUM to FUNCTION_ARG, because we would
get double copies of any offsets generated for small structs
passed in registers. */
CUMULATIVE_ARGS temp;
temp = *cum;
......@@ -8569,7 +8556,7 @@ build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
&& strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
return 0;
/* This code will only work for o32 and o64 abis. The other ABI's
/* This code will only work for o32 and o64 abis. The other ABI's
require more sophisticated support. */
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
abort ();
......@@ -9000,7 +8987,7 @@ mips16_optimize_gp (first)
emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
force_const_mem (Pmode, sym)),
next);
PUT_CODE (insn, NOTE);
NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
NOTE_SOURCE_FILE (insn) = 0;
......@@ -9365,10 +9352,10 @@ machine_dependent_reorg (first)
constants = NULL;
first_constant_ref = -1;
}
if (constants != NULL
&& (NEXT_INSN (insn) == NULL
|| (first_constant_ref >= 0
&& (NEXT_INSN (insn) == NULL
|| (first_constant_ref >= 0
&& (((addr - first_constant_ref)
+ 2 /* for alignment */
+ 2 /* for a short jump insn */
......@@ -9380,7 +9367,7 @@ machine_dependent_reorg (first)
emit a barrier now. */
rtx label, jump, barrier;
label = gen_label_rtx ();
jump = emit_jump_insn_after (gen_jump (label), insn);
JUMP_LABEL (jump) = label;
......@@ -9422,7 +9409,7 @@ highpart_shift_operator (x, mode)
|| code == ROTATE);
}
/* Return the length of INSN. LENGTH is the initial length computed by
/* Return the length of INSN. LENGTH is the initial length computed by
attributes in the machine-description file. */
int
......@@ -9434,7 +9421,7 @@ mips_adjust_insn_length (insn, length)
of a sequence. A conditional jump normally has a delay slot, but
does not on MIPS16. */
if (simplejump_p (insn)
|| (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
|| (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
|| GET_CODE (insn) == CALL_INSN)))
length += 4;
......@@ -9445,7 +9432,7 @@ mips_adjust_insn_length (insn, length)
return length;
}
/* Output assembly instructions to peform a conditional branch.
/* Output assembly instructions to peform a conditional branch.
INSN is the branch instruction. OPERANDS[0] is the condition.
OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
......@@ -9460,8 +9447,8 @@ mips_adjust_insn_length (insn, length)
That tells us whether to generate a simple conditional branch, or a
reversed conditional branch around a `jr' instruction. */
char *
mips_output_conditional_branch (insn,
operands,
mips_output_conditional_branch (insn,
operands,
two_operands_p,
float_p,
inverted_p,
......@@ -9537,7 +9524,7 @@ mips_output_conditional_branch (insn,
equality comparisons are done between two operands, and therefore
do not require a `z' in the assembly language output. */
need_z_p = (!float_p && code != EQ && code != NE);
/* For comparisons against zero, the zero is not provided
/* For comparisons against zero, the zero is not provided
explicitly. */
if (need_z_p)
op2 = "";
......@@ -9546,7 +9533,7 @@ mips_output_conditional_branch (insn,
strcat to add to it. */
buffer[0] = '\0';
switch (length)
switch (length)
{
case 4:
case 8:
......@@ -9585,18 +9572,18 @@ mips_output_conditional_branch (insn,
wait until the next instruction is output; it might be a
macro and take up more than four bytes. Once again, we see
why we want to eliminate macros.)
If the branch is annulled, we jump four more bytes that we
would otherwise; that way we skip the annulled instruction
in the delay slot. */
const char *target
const char *target
= ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
char *c;
strcpy (buffer, "%(%<");
c = strchr (buffer, '\0');
/* Generate the reversed comparision. This takes four
/* Generate the reversed comparision. This takes four
bytes. */
if (float_p)
sprintf (c, "%%*b%s\t%%Z2%s",
......@@ -9652,7 +9639,7 @@ mips_output_conditional_branch (insn,
generate only a four-byte sequence, rather than eight, and
there seems to be no way to tell it not to. Thus, we can't
just use a `.+x' addressing form; we don't know what value
to give for `x'.
to give for `x'.
So, we resort to using the explicit relocation syntax
available in the assembler and do:
......@@ -9667,7 +9654,7 @@ mips_output_conditional_branch (insn,
anything. */
/* The target of the reversed branch. */
const char *target
const char *target
= ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
......@@ -9675,7 +9662,7 @@ mips_output_conditional_branch (insn,
strcpy (buffer, "%(%<%[");
c = strchr (buffer, '\0');
/* Generate the reversed comparision. This takes four
/* Generate the reversed comparision. This takes four
bytes. */
if (float_p)
sprintf (c, "%%*b%s\t%%Z2%s",
......@@ -9730,3 +9717,88 @@ mips_add_gc_roots ()
ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
}
static enum processor_type
mips_parse_cpu (cpu_string)
const char *cpu_string;
{
const char *p = cpu_string;
int seen_v = 0;
enum processor_type cpu;
/* We need to cope with the various "vr" prefixes for the NEC 4300
and 4100 processors. */
if (*p == 'v' || *p == 'V')
seen_v = 1, p++;
if (*p == 'r' || *p == 'R')
p++;
/* Since there is no difference between a R2000 and R3000 in
terms of the scheduler, we collapse them into just an R3000. */
cpu = PROCESSOR_DEFAULT;
switch (*p)
{
case '2':
if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
cpu = PROCESSOR_R3000;
break;
case '3':
if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
cpu = PROCESSOR_R3000;
else if (!strcmp (p, "3900"))
cpu = PROCESSOR_R3900;
break;
case '4':
if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
cpu = PROCESSOR_R4000;
/* The vr4100 is a non-FP ISA III processor with some extra
instructions. */
else if (!strcmp (p, "4100"))
cpu = PROCESSOR_R4100;
/* The vr4300 is a standard ISA III processor, but with a different
pipeline. */
else if (!strcmp (p, "4300"))
cpu = PROCESSOR_R4300;
/* The r4400 is exactly the same as the r4000 from the compiler's
viewpoint. */
else if (!strcmp (p, "4400"))
cpu = PROCESSOR_R4000;
else if (!strcmp (p, "4600"))
cpu = PROCESSOR_R4600;
else if (!strcmp (p, "4650"))
cpu = PROCESSOR_R4650;
break;
case '5':
if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
cpu = PROCESSOR_R5000;
break;
case '6':
if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
cpu = PROCESSOR_R6000;
break;
case '8':
if (!strcmp (p, "8000"))
cpu = PROCESSOR_R8000;
break;
case 'o':
if (!strcmp (p, "orion"))
cpu = PROCESSOR_R4600;
break;
}
if (seen_v
&& cpu != PROCESSOR_R4300
&& cpu != PROCESSOR_R4100
&& cpu != PROCESSOR_R5000)
cpu = PROCESSOR_DEFAULT;
return cpu;
}
gcc/config/mips/mips.h
......@@ -133,13 +133,17 @@ extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
extern int mips_dbx_regno[]; /* Map register # to debug register # */
extern struct rtx_def *branch_cmp[2]; /* operands for compare */
extern enum cmp_type branch_type; /* what type of branch to use */
extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
extern enum processor_type mips_arch; /* which cpu to codegen for */
extern enum processor_type mips_tune; /* which cpu to schedule for */
extern enum processor_type mips_cpu; /* historical codegen/sched */
extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
extern int mips_isa; /* architectural level */
extern int mips16; /* whether generating mips16 code */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
extern const char *mips_arch_string; /* for -march=<xxx> */
extern const char *mips_tune_string; /* for -mtune=<xxx> */
extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
......@@ -212,14 +216,13 @@ extern void sbss_section PARAMS ((void));
#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
#define MASK_MIPS16 0x00200000 /* Generate mips16 code */
#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV \
0x00400000 /* divide by zero checking */
0x00200000 /* divide by zero checking */
#define MASK_CHECK_RANGE_DIV \
0x00800000 /* divide result range checking */
0x00400000 /* divide result range checking */
#define MASK_UNINIT_CONST_IN_RODATA \
0x01000000 /* Store uninitialized
0x00800000 /* Store uninitialized
consts in rodata */
/* Debug switches, not documented */
......@@ -246,9 +249,6 @@ extern void sbss_section PARAMS ((void));
/* Mips vs. GNU linker */
#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
/* generate mips 3900 insns */
#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
/* Mips vs. GNU assembler */
#define TARGET_GAS (target_flags & MASK_GAS)
#define TARGET_MIPS_AS (!TARGET_GAS)
......@@ -330,6 +330,19 @@ extern void sbss_section PARAMS ((void));
/* Generate mips16 code */
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_cpu == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_cpu == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_cpu == PROCESSOR_R4000)
#define TUNE_MIPS5000 (mips_cpu == PROCESSOR_R5000)
#define TUNE_MIPS6000 (mips_cpu == PROCESSOR_R6000)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
......@@ -430,10 +443,10 @@ extern void sbss_section PARAMS ((void));
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
{"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
N_("Optimize for 4650")}, \
{"3900", MASK_MIPS3900, \
{"3900", 0, \
N_("Optimize for 3900")}, \
{"4650", 0, \
N_("Optimize for 4650")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
......@@ -466,7 +479,7 @@ extern void sbss_section PARAMS ((void));
| TARGET_CPU_DEFAULT \
| TARGET_ENDIAN_DEFAULT), \
NULL}, \
}
}
/* Default target_flags if no switches are specified */
......@@ -550,7 +563,7 @@ extern void sbss_section PARAMS ((void));
initializer with a subgrouping for each command option.
Each subgrouping contains a string constant, that defines the
fixed part of the option name, and the address of a variable.
fixed part of the option name, and the address of a variable.
The variable, type `char *', is set to the variable part of the
given option if the fixed part matches. The actual option name
is made by appending `-m' to the specified name.
......@@ -567,8 +580,12 @@ extern void sbss_section PARAMS ((void));
SUBTARGET_TARGET_OPTIONS \
{ "cpu=", &mips_cpu_string, \
N_("Specify CPU for scheduling purposes")}, \
{ "tune=", &mips_tune_string, \
N_("Specify CPU for scheduling purposes")}, \
{ "arch=", &mips_arch_string, \
N_("Specify CPU for code generation purposes")}, \
{ "ips", &mips_isa_string, \
N_("Specify MIPS ISA")}, \
N_("Specify a Standard MIPS ISA")}, \
{ "entry", &mips_entry_string, \
N_("Use mips16 entry/exit psuedo ops")}, \
{ "no-mips16", &mips_no_mips16_string, \
......@@ -580,7 +597,7 @@ extern void sbss_section PARAMS ((void));
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
/* Generate three-operand multiply instructions for both SImode and DImode. */
#define GENERATE_MULT3 (TARGET_MIPS3900 \
......@@ -596,8 +613,11 @@ extern void sbss_section PARAMS ((void));
#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
)
/* ISA has branch likely instructions (eg. mips2). */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
/* ISA has branch likely instructions (eg. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
/* || TARGET_MIPS3900 */)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
......@@ -615,7 +635,7 @@ extern void sbss_section PARAMS ((void));
/* This is a catch all for the other new mips4 instructions: indexed load and
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
and the FP recip and recip sqrt instructions */
#define ISA_HAS_FP4 (mips_isa == 4 \
)
......@@ -791,7 +811,7 @@ while (0)
/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
assembler. */
#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
GAS_ASM_SPEC as the default, depending upon the value of
......@@ -909,6 +929,16 @@ while (0)
#define SUBTARGET_CC1_SPEC ""
#endif
/* Deal with historic options. */
#ifndef CC1_CPU_SPEC
#define CC1_CPU_SPEC "\
%{!mcpu*: \
%{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
%n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
%{m4650:-march=r4650 -mmad -msingle-float \
%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
#endif
/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
#ifndef CC1_SPEC
......@@ -920,15 +950,14 @@ while (0)
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{mint64|mlong64|mlong32:-mexplicit-type-size }\
%{m4650:-mcpu=r4650} \
%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{pic-none: -mno-half-pic} \
%{pic-lib: -mhalf-pic} \
%{pic-extern: -mhalf-pic} \
%{pic-calls: -mhalf-pic} \
%{save-temps: } \
%(subtarget_cc1_spec) "
%(subtarget_cc1_spec) \
%(cc1_cpu_spec)"
#endif
/* Preprocessor specs. */
......@@ -1111,7 +1140,7 @@ while (0)
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
/* Offsets recorded in opcodes are a multiple of this alignment factor.
/* Offsets recorded in opcodes are a multiple of this alignment factor.
The default for this in 64-bit mode is 8, which causes problems with
SFmode register saves. */
#define DWARF_CIE_DATA_ALIGNMENT 4
......@@ -1490,7 +1519,7 @@ do { \
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none.
done, NIL if none.
When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
moves. All other referces are zero extended. */
......@@ -1499,7 +1528,7 @@ do { \
? SIGN_EXTEND : ZERO_EXTEND)
/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
extension may differ from that of the type.
......@@ -1731,7 +1760,7 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
/* The register number of the register used to address a table of
static data addresses in memory. In some cases this register is
defined by a processor's "application binary interface" (ABI).
defined by a processor's "application binary interface" (ABI).
When this macro is defined, RTL is generated for this register
once, as with the stack pointer and frame pointer registers. If
this macro is not defined, it is up to the machine-dependent
......@@ -1989,7 +2018,7 @@ extern enum reg_class mips_char_to_class[];
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
/* Letters in the range `Q' through `U' may be defined in a
machine-dependent fashion to stand for arbitrary operand types.
machine-dependent fashion to stand for arbitrary operand types.
The machine description macro `EXTRA_CONSTRAINT' is passed the
operand as its first argument and the constraint letter as its
second operand.
......@@ -2181,7 +2210,7 @@ extern struct mips_frame_info current_frame_info;
On some machines, the position of the argument pointer is not
known until the compilation is completed. In such a case, a
separate hard register must be used for the argument pointer.
separate hard register must be used for the argument pointer.
This register can be eliminated by replacing it with either the
frame pointer or the argument pointer, depending on whether or not
the frame pointer has been eliminated.
......@@ -2333,9 +2362,9 @@ extern struct mips_frame_info current_frame_info;
((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
/* Define this if it is the responsibility of the caller to
allocate the area reserved for arguments passed in registers.
allocate the area reserved for arguments passed in registers.
If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
of this macro is to determine whether the space is included in
of this macro is to determine whether the space is included in
`current_function_outgoing_args_size'. */
#define OUTGOING_REG_PARM_STACK_SPACE
......@@ -2496,7 +2525,7 @@ typedef struct mips_args {
int fp_code; /* Mode of FP arguments (mips16) */
unsigned int num_adjusts; /* number of adjustments made */
/* Adjustments made to args pass in regs. */
/* ??? The size is doubled to work around a
/* ??? The size is doubled to work around a
bug in the code that sets the adjustments
in function_arg. */
struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
......@@ -2634,7 +2663,7 @@ typedef struct mips_args {
/* A C statement to output, on the stream FILE, assembler code for a
block of data that contains the constant parts of a trampoline.
block of data that contains the constant parts of a trampoline.
This code should not include a label--the label is taken care of
automatically. */
......@@ -2684,7 +2713,7 @@ typedef struct mips_args {
#define CACHE_FLUSH_FUNC "_flush_cache"
#endif
/* A C statement to initialize the variable parts of a trampoline.
/* A C statement to initialize the variable parts of a trampoline.
ADDR is an RTX for the address of the trampoline; FNADDR is an
RTX for the address of the nested function; STATIC_CHAIN is an
RTX for the static chain value that should be passed to the
......@@ -2782,7 +2811,7 @@ typedef struct mips_args {
to understand.
This macro must exist in two variants: a strict variant and a
non-strict one. The strict variant is used in the reload pass.
non-strict one. The strict variant is used in the reload pass.
It must be defined so that any pseudo-register that has not been
allocated a hard register is considered a memory reference. In
contexts where some kind of register is required, a
......@@ -2819,7 +2848,7 @@ typedef struct mips_args {
On some machines, whether a symbolic address is legitimate
depends on the section that the address refers to. On these
machines, define the macro `ENCODE_SECTION_INFO' to store the
information into the `symbol_ref', and then check for it here.
information into the `symbol_ref', and then check for it here.
When you see a `const', you will have to look inside it to find
the `symbol_ref' in order to determine the section. */
......@@ -2880,7 +2909,7 @@ typedef struct mips_args {
to be generated at present. Also, the MIPS assembler does not
grok li.d Infinity. */
/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
Note that the Irix 6 assembler problem may already be fixed.
Note also that the GET_CODE (X) == CONST test catches the mips16
gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
......@@ -2932,7 +2961,7 @@ typedef struct mips_args {
When PIC, convert addresses of the form memory (symbol+large int) to
memory (reg+large int). */
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ \
......@@ -3033,7 +3062,7 @@ typedef struct mips_args {
function named by the symbol (such as what section it is in).
The macro definition, if any, is executed immediately after the
rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
The value of the rtl will be a `mem' whose address is a
`symbol_ref'.
......@@ -3043,7 +3072,7 @@ typedef struct mips_args {
information).
The best way to modify the name string is by adding text to the
beginning, with suitable punctuation to prevent any ambiguity.
beginning, with suitable punctuation to prevent any ambiguity.
Allocate the new name in `saveable_obstack'. You will have to
modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
and output the name accordingly.
......@@ -3062,7 +3091,7 @@ typedef struct mips_args {
constants which are put in the .text section. We also record the
total length of all such strings; this total is used to decide
whether we need to split the constant table, and need not be
precisely correct.
precisely correct.
When not mips16 code nor embedded PIC, if a symbol is in a
gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
......@@ -3455,10 +3484,10 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode || xmode == DFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (3); \
else \
return COSTS_N_INSNS (6); \
......@@ -3481,11 +3510,11 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900 \
|| mips_cpu == PROCESSOR_R5000) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (4); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
......@@ -3493,23 +3522,23 @@ while (0)
\
if (xmode == DFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900 \
|| mips_cpu == PROCESSOR_R5000) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
} \
\
if (mips_cpu == PROCESSOR_R3000) \
if (TUNE_MIPS3000) \
return COSTS_N_INSNS (12); \
else if (mips_cpu == PROCESSOR_R3900) \
else if (TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (17); \
else if (mips_cpu == PROCESSOR_R5000) \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (10); \
......@@ -3521,10 +3550,10 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (12); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (15); \
else \
return COSTS_N_INSNS (23); \
......@@ -3532,10 +3561,10 @@ while (0)
\
if (xmode == DFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (19); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (16); \
else \
return COSTS_N_INSNS (36); \
......@@ -3545,12 +3574,12 @@ while (0)
\
case UDIV: \
case UMOD: \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R3900) \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (35); \
else if (mips_cpu == PROCESSOR_R6000) \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (38); \
else if (mips_cpu == PROCESSOR_R5000) \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (36); \
else \
return COSTS_N_INSNS (69); \
......@@ -3587,7 +3616,7 @@ while (0)
used.
For example, suppose an address that is equal to the sum of a
register and a constant is used twice in the same basic block.
register and a constant is used twice in the same basic block.
When this macro is not defined, the address will be computed in
a register and memory references will be indirect through that
register. On machines where the cost of the addressing mode
......@@ -3607,7 +3636,7 @@ while (0)
defining `ADDRESS_COST' to reflect this can cause two registers
to be live over a region of code where only one would have been
if `ADDRESS_COST' were not defined in that manner. This effect
should be considered in the definition of this macro.
should be considered in the definition of this macro.
Equivalent costs should probably only be given to addresses with
different numbers of registers on machines with lots of registers.
......@@ -3668,7 +3697,7 @@ while (0)
/* ??? Fix this to be right for the R8000. */
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
(((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
(((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
+ memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
/* Define if copies to/from condition code registers should be avoided.
......@@ -3684,7 +3713,7 @@ while (0)
/* ??? Fix this to be right for the R8000. */
#define BRANCH_COST \
((! TARGET_MIPS16 \
&& (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
&& (TUNE_MIPS4000 || TUNE_MIPS6000)) \
? 2 : 1)
/* A C statement (sans semicolon) to update the integer variable COST
......@@ -3720,7 +3749,7 @@ while (0)
Defining this macro does not affect the generated code (however,
incorrect definitions that omit an rtl code that may be matched
by the predicate can cause the compiler to malfunction).
by the predicate can cause the compiler to malfunction).
Instead, it allows the table built by `genrecog' to be more
compact and efficient, thus speeding up the compiler. The most
important predicates to include in the list specified by this
......@@ -4138,7 +4167,7 @@ do { \
/* A C statement (sans semicolon) to output to the stdio stream
STREAM any text necessary for declaring the name NAME of an
initialized variable which is being defined. This macro must
output the label definition (perhaps using `ASM_OUTPUT_LABEL').
output the label definition (perhaps using `ASM_OUTPUT_LABEL').
The argument DECL is the `VAR_DECL' tree node representing the
variable.
......@@ -4274,11 +4303,11 @@ do { \
fprintf (STREAM, "\n"); \
} while (0)
/* Likewise for 64 bit, `char' and `short' constants.
/* Likewise for 64 bit, `char' and `short' constants.
FIXME: operand_subword can't handle some complex constant expressions
that output_addr_const can (for example it does not call
simplify_subtraction). Since GAS can handle dword, even for mipsII,
simplify_subtraction). Since GAS can handle dword, even for mipsII,
rely on that to avoid operand_subword for most of the cases where this
matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
or the same case with the type of 'i' changed to long long.
......
gcc/config/mips/mips.md
......@@ -1626,7 +1626,7 @@
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
if (mips_cpu != PROCESSOR_R4300)
if (TARGET_MIPS4300)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
......@@ -1637,7 +1637,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")])
......@@ -1646,7 +1646,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
"*
{
output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
......@@ -1665,7 +1665,7 @@
"TARGET_HARD_FLOAT"
"
{
if (mips_cpu != PROCESSOR_R4300)
if (!TARGET_MIPS4300)
emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
......@@ -1676,7 +1676,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
"TARGET_HARD_FLOAT && !TARGET_MIPS4300"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
......@@ -1685,7 +1685,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
"TARGET_HARD_FLOAT && TARGET_MIPS4300"
"*
{
output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
......@@ -1713,7 +1713,7 @@
{
if (HAVE_mulsi3_mult3)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
else if (!TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
......@@ -1746,7 +1746,7 @@
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=a"))]
"mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
"!TARGET_MIPS4000 || TARGET_MIPS16"
"mult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
......@@ -1758,7 +1758,7 @@
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=l"))
(clobber (match_scratch:SI 5 "=a"))]
"mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
"TARGET_MIPS4000 && !TARGET_MIPS16"
"*
{
rtx xoperands[10];
......@@ -1855,7 +1855,7 @@
"
{
if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
if (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
......@@ -1873,7 +1873,7 @@
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16"
"TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
"dmult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
......@@ -1885,7 +1885,7 @@
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))
(clobber (match_scratch:DI 5 "=a"))]
"TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)"
"TARGET_64BIT && (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)"
"*
{
if (GENERATE_MULT3)
......
gcc/config/mips/r3900.h
......@@ -43,7 +43,6 @@ Boston, MA 02111-1307, USA. */
%{msingle-float:%{msoft-float: \
%e-msingle-float and -msoft-float can not both be specified.}}"
#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900)
#define MIPS_CPU_STRING_DEFAULT "R3900"
#define MIPS_ISA_DEFAULT 1
......
gcc/doc/invoke.texi
......@@ -447,8 +447,8 @@ in the following sections.
@emph{MIPS Options}
@gccoptlist{
-mabicalls -mcpu=@var{cpu-type} @gol
-membedded-data -muninit-const-in-rodata @gol
-mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol
-mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol
-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol
......@@ -935,9 +935,16 @@ names @samp{c9x} and @samp{iso9899:199x} are deprecated.
Default, ISO C89 plus GNU extensions (including some C99 features).
@item gnu99
@itemx gnu9x
ISO C99 plus GNU extensions. When ISO C99 is fully implemented in GCC,
this will become the default. The name @samp{gnu9x} is deprecated.
iso9899:1999 + gnu extensions
@item iso9899:199x
same as @option{-std=iso9899:1999}, deprecated
@item c9x
same as @option{-std=iso9899:1999}, deprecated
@item gnu9x
same as @option{-std=gnu99}, deprecated
@end table
......@@ -3804,7 +3811,7 @@ optimization. If more memory than specified is required, the
optimization will not be done.
@item max-gcse-passes
The maximum number of passes of GCSE to run.
The maximum number of passes of GCSE to run.
@item max-inline-insns
If an function contains more than this many instructions, it
......@@ -4451,7 +4458,7 @@ Variables}.
As a special kludge, if the path provided by @option{-B} is
@file{[dir/]stage@var{N}/}, where @var{N} is a number in the range 0 to
9, then it will be replaced by @file{[dir/]include}. This is to help
with boot-strapping the compiler.
with boot-strapping the compiler.
@item -specs=@var{file}
@opindex specs
......@@ -7031,8 +7038,19 @@ option @option{-mhc-struct-return}.
These @samp{-m} options are defined for the MIPS family of computers:
@table @gcctabopt
@item -mcpu=@var{cpu-type}
@opindex mcpu
@item -march=@var{cpu-type}
@opindex march
Assume the defaults for the machine type @var{cpu-type} when generating
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc.
@item -mtune=@var{cpu-type}
@opindex mtune
Assume the defaults for the machine type @var{cpu-type} when scheduling
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
......@@ -7045,6 +7063,10 @@ chip, the compiler will not generate any code that does not meet level 1
of the MIPS ISA (instruction set architecture) without a @option{-mipsX}
or @option{-mabi} switch being used.
@item -mcpu=@var{cpu-type}
@opindex mcpu
This is identical to specifying both @option{-march} and @option{-mtune}.
@item -mips1
@opindex mips1
Issue instructions from level 1 of the MIPS ISA@. This is the default.
......
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