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riscv-gcc-1
Commit 7dac2f89 by Eric Christopher
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[multiple changes] 

2001-07-05  Eric Christopher  <echristo@redhat.com>

        * config/mips/mips.h (MASK_MIPS3900): Remove.
        (MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
        MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
        (TARGET_MIPS3900): Change to use mips_arch.
        (TARGET_MIPS4000): New.
        (TARGET_MIPS4100): New.
        (TARGET_MIPS4300): New.
        (TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
        (SUBTARGET_TARGET_OPTIONS): Add -march. Change help text
        for -mipsX.
        (GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
        (ISA_HAS_BRANCHLIKELY): To here.
        (CC1_CPU_SPEC):  New.
        (CC1_SPEC): Use here.  Remove 4650 and 3900 options.
        (mips_arch_string): Declare.
        (mips_arch): Declare.
        (TARGET_OPTIONS): Add -march and -mtune.

        * config/mips/mips.c (mips_arch_string): New.
        (mips_arch): New.
        (override_options): Handle -march for codegen and -mtune
        for scheduling. Use mips_arch. Move tx39 target default here.
        (mips_parse_cpu): Move error message to override_options.

        * config/mips/r3900.h (TARGET_DEFAULT): Remove.

        * config/mips/mips.md: Use TARGET_MIPS4000 and TARGET_MIPS4300.

        * doc/invoke.texi (Option Summary): Add -march and -mtune entries.
        (MIPS Options): Ditto.  Change mcpu entry to historical text.

2001-07-05  H.J. Lu  (hjl@gnu.org)

        * config/mips/mips.c (mips_parse_cpu): New function to parse
        -march=*/-mcpu=*.

From-SVN: r43803
parent 8a749647
Showing with 83 additions and 24 deletions
gcc/ChangeLog
2001-07-05 Eric Christopher <echristo@redhat.com>
* config/mips/mips.h (MASK_MIPS3900): Remove.
(MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
(TARGET_MIPS3900): Change to use mips_arch.
(TARGET_MIPS4000): New.
(TARGET_MIPS4100): New.
(TARGET_MIPS4300): New.
(TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
(SUBTARGET_TARGET_OPTIONS): Add -march. Change help text
for -mipsX.
(GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
(ISA_HAS_BRANCHLIKELY): To here.
(CC1_CPU_SPEC): New.
(CC1_SPEC): Use here. Remove 4650 and 3900 options.
(mips_arch_string): Declare.
(mips_arch): Declare.
(TARGET_OPTIONS): Add -march and -mtune.
* config/mips/mips.c (mips_arch_string): New.
(mips_arch): New.
(override_options): Handle -march for codegen and -mtune
for scheduling. Use mips_arch. Move tx39 target default here.
(mips_parse_cpu): Move error message to override_options.
* config/mips/r3900.h (TARGET_DEFAULT): Remove.
* config/mips/mips.md: Use TARGET_MIPS4000 and TARGET_MIPS4300.
* doc/invoke.texi (Option Summary): Add -march and -mtune entries.
(MIPS Options): Ditto. Change mcpu entry to historical text.
2001-07-05 H.J. Lu (hjl@gnu.org)
* config/mips/mips.c (mips_parse_cpu): New function to parse
-march=*/-mcpu=*.
2001-07-05 Jim Wilson <wilson@redhat.com> 2001-07-05 Jim Wilson <wilson@redhat.com>
* config/ia64/lib1funcs.asm: Revert 2001-07-02 change. * config/ia64/lib1funcs.asm: Revert 2001-07-02 change.
...@@ -10,8 +48,8 @@ ...@@ -10,8 +48,8 @@
2001-07-04 Stephane Carrez <Stephane.Carrez@worldnet.fr> 2001-07-04 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/m68hc11.md ("*ashlsi3"): Operand 1 can be a memory * config/m68hc11/m68hc11.md ("*ashlsi3"): Operand 1 can be a memory
reference using the stack pointer, adjust it since we push Y reference using the stack pointer, adjust it since we push Y
temporarily. temporarily.
("*ashrsi3"): Likewise. ("*ashrsi3"): Likewise.
("*lshrsi3"): Likewise. ("*lshrsi3"): Likewise.
......
gcc/config/mips/mips.md
...@@ -1626,7 +1626,7 @@ ...@@ -1626,7 +1626,7 @@
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
" "
{ {
if (mips_cpu != PROCESSOR_R4300) if (TARGET_MIPS4300)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2])); emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2])); emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
...@@ -1637,7 +1637,7 @@ ...@@ -1637,7 +1637,7 @@
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f") (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
"mul.d\\t%0,%1,%2" "mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul") [(set_attr "type" "fmul")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -1646,7 +1646,7 @@ ...@@ -1646,7 +1646,7 @@
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f") (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
"* "*
{ {
output_asm_insn (\"mul.d\\t%0,%1,%2\", operands); output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
...@@ -1665,7 +1665,7 @@ ...@@ -1665,7 +1665,7 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
" "
{ {
if (mips_cpu != PROCESSOR_R4300) if (!TARGET_MIPS4300)
emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2])); emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
else else
emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2])); emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
...@@ -1676,7 +1676,7 @@ ...@@ -1676,7 +1676,7 @@
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f") (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300" "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
"mul.s\\t%0,%1,%2" "mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul") [(set_attr "type" "fmul")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
...@@ -1685,7 +1685,7 @@ ...@@ -1685,7 +1685,7 @@
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f") (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300" "TARGET_HARD_FLOAT && TARGET_MIPS4300"
"* "*
{ {
output_asm_insn (\"mul.s\\t%0,%1,%2\", operands); output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
...@@ -1713,7 +1713,7 @@ ...@@ -1713,7 +1713,7 @@
{ {
if (HAVE_mulsi3_mult3) if (HAVE_mulsi3_mult3)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2])); emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16) else if (!TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2])); emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
else else
emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2])); emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
...@@ -1746,7 +1746,7 @@ ...@@ -1746,7 +1746,7 @@
(match_operand:SI 2 "register_operand" "d"))) (match_operand:SI 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=a"))] (clobber (match_scratch:SI 4 "=a"))]
"mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16" "!TARGET_MIPS4000 || TARGET_MIPS16"
"mult\\t%1,%2" "mult\\t%1,%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
...@@ -1758,7 +1758,7 @@ ...@@ -1758,7 +1758,7 @@
(clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=l")) (clobber (match_scratch:SI 4 "=l"))
(clobber (match_scratch:SI 5 "=a"))] (clobber (match_scratch:SI 5 "=a"))]
"mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16" "TARGET_MIPS4000 && !TARGET_MIPS16"
"* "*
{ {
rtx xoperands[10]; rtx xoperands[10];
...@@ -1855,7 +1855,7 @@ ...@@ -1855,7 +1855,7 @@
" "
{ {
if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) if (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2])); emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
else else
emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2])); emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
...@@ -1873,7 +1873,7 @@ ...@@ -1873,7 +1873,7 @@
(match_operand:DI 2 "register_operand" "d"))) (match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))] (clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
"dmult\\t%1,%2" "dmult\\t%1,%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
...@@ -1885,7 +1885,7 @@ ...@@ -1885,7 +1885,7 @@
(clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l")) (clobber (match_scratch:DI 4 "=l"))
(clobber (match_scratch:DI 5 "=a"))] (clobber (match_scratch:DI 5 "=a"))]
"TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)" "TARGET_64BIT && (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)"
"* "*
{ {
if (GENERATE_MULT3) if (GENERATE_MULT3)
......
gcc/config/mips/r3900.h
...@@ -43,7 +43,6 @@ Boston, MA 02111-1307, USA. */ ...@@ -43,7 +43,6 @@ Boston, MA 02111-1307, USA. */
%{msingle-float:%{msoft-float: \ %{msingle-float:%{msoft-float: \
%e-msingle-float and -msoft-float can not both be specified.}}" %e-msingle-float and -msoft-float can not both be specified.}}"
#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900)
#define MIPS_CPU_STRING_DEFAULT "R3900" #define MIPS_CPU_STRING_DEFAULT "R3900"
#define MIPS_ISA_DEFAULT 1 #define MIPS_ISA_DEFAULT 1
......
gcc/doc/invoke.texi
...@@ -447,8 +447,8 @@ in the following sections. ...@@ -447,8 +447,8 @@ in the following sections.
@emph{MIPS Options} @emph{MIPS Options}
@gccoptlist{ @gccoptlist{
-mabicalls -mcpu=@var{cpu-type} @gol -mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol
-membedded-data -muninit-const-in-rodata @gol -mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol
-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol -membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol -mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol -mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol
...@@ -935,9 +935,16 @@ names @samp{c9x} and @samp{iso9899:199x} are deprecated. ...@@ -935,9 +935,16 @@ names @samp{c9x} and @samp{iso9899:199x} are deprecated.
Default, ISO C89 plus GNU extensions (including some C99 features). Default, ISO C89 plus GNU extensions (including some C99 features).
@item gnu99 @item gnu99
@itemx gnu9x iso9899:1999 + gnu extensions
ISO C99 plus GNU extensions. When ISO C99 is fully implemented in GCC,
this will become the default. The name @samp{gnu9x} is deprecated. @item iso9899:199x
same as @option{-std=iso9899:1999}, deprecated
@item c9x
same as @option{-std=iso9899:1999}, deprecated
@item gnu9x
same as @option{-std=gnu99}, deprecated
@end table @end table
...@@ -3804,7 +3811,7 @@ optimization. If more memory than specified is required, the ...@@ -3804,7 +3811,7 @@ optimization. If more memory than specified is required, the
optimization will not be done. optimization will not be done.
@item max-gcse-passes @item max-gcse-passes
The maximum number of passes of GCSE to run. The maximum number of passes of GCSE to run.
@item max-inline-insns @item max-inline-insns
If an function contains more than this many instructions, it If an function contains more than this many instructions, it
...@@ -4451,7 +4458,7 @@ Variables}. ...@@ -4451,7 +4458,7 @@ Variables}.
As a special kludge, if the path provided by @option{-B} is As a special kludge, if the path provided by @option{-B} is
@file{[dir/]stage@var{N}/}, where @var{N} is a number in the range 0 to @file{[dir/]stage@var{N}/}, where @var{N} is a number in the range 0 to
9, then it will be replaced by @file{[dir/]include}. This is to help 9, then it will be replaced by @file{[dir/]include}. This is to help
with boot-strapping the compiler. with boot-strapping the compiler.
@item -specs=@var{file} @item -specs=@var{file}
@opindex specs @opindex specs
...@@ -7031,8 +7038,19 @@ option @option{-mhc-struct-return}. ...@@ -7031,8 +7038,19 @@ option @option{-mhc-struct-return}.
These @samp{-m} options are defined for the MIPS family of computers: These @samp{-m} options are defined for the MIPS family of computers:
@table @gcctabopt @table @gcctabopt
@item -mcpu=@var{cpu-type}
@opindex mcpu @item -march=@var{cpu-type}
@opindex march
Assume the defaults for the machine type @var{cpu-type} when generating
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc.
@item -mtune=@var{cpu-type}
@opindex mtune
Assume the defaults for the machine type @var{cpu-type} when scheduling Assume the defaults for the machine type @var{cpu-type} when scheduling
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000}, instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400}, @samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
...@@ -7045,6 +7063,10 @@ chip, the compiler will not generate any code that does not meet level 1 ...@@ -7045,6 +7063,10 @@ chip, the compiler will not generate any code that does not meet level 1
of the MIPS ISA (instruction set architecture) without a @option{-mipsX} of the MIPS ISA (instruction set architecture) without a @option{-mipsX}
or @option{-mabi} switch being used. or @option{-mabi} switch being used.
@item -mcpu=@var{cpu-type}
@opindex mcpu
This is identical to specifying both @option{-march} and @option{-mtune}.
@item -mips1 @item -mips1
@opindex mips1 @opindex mips1
Issue instructions from level 1 of the MIPS ISA@. This is the default. Issue instructions from level 1 of the MIPS ISA@. This is the default.
......
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