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riscv-gcc-1
Commit 7d83f4f5 by Uros Bizjak
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alpha.c: Use REG_P... 

	* config/alpha/alpha.c: Use REG_P, MEM_P, CONST_INT_P, JUMP_P,
	NONJUMP_INSN_P, CALL_P, LABEL_P and NOTE_P predicates instead of
	GET_CODE macro.  Use IN_RANGE macro where appropriate.
	* config/alpha/alpha.h: Ditto.
	* config/alpha/alpha.md: Ditto.
	* config/alpha/constraints.md: Ditto.
	* config/alpha/predicates.md: Ditto.

From-SVN: r146550
parent a8e05f92
Showing with 66 additions and 58 deletions
gcc/ChangeLog
2009-04-22 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.c: Use REG_P, MEM_P, CONST_INT_P, JUMP_P,
NONJUMP_INSN_P, CALL_P, LABEL_P and NOTE_P predicates instead of
GET_CODE macro. Use IN_RANGE macro where appropriate.
* config/alpha/alpha.h: Ditto.
* config/alpha/alpha.md: Ditto.
* config/alpha/constraints.md: Ditto.
* config/alpha/predicates.md: Ditto.
2009-04-22 Paolo Bonzini <bonzini@gnu.org>
* defaults.h (GO_IF_MODE_DEPENDENT_ADDRESS): Provide empty default.
......@@ -40,8 +50,7 @@
(find_basic_blocks_1): Delete.
(find_basic_blocks): Delete.
* except.c (finish_eh_generation): Make static. Move comment from
except.h here. Remove find_basic_blocks references from
comments.
except.h here. Remove find_basic_blocks references from comments.
* except.h (finish_eh_generation): Delete.
* basic-block.h (find_basic_blocks): Delete.
* config/sh/sh.c (sh_output_mi_thunk): Delete a "#if 0" block.
......@@ -222,8 +231,8 @@
* tree-switch-conversion.c (build_constructors): Split a long line.
(constructor_contains_same_values_p): New function.
(build_one_array): Create assigns of constants if possible, do not call
mark_sym_for_renaming, call update_stmt.
(build_one_array): Create assigns of constants if possible, do not
call mark_sym_for_renaming, call update_stmt.
(build_arrays): Call make_ssa_name (create_tmp_var ()) instead of
make_rename_temp. Do not call mark_symbols_for_renaming, call
update_stmt.
......@@ -237,8 +246,7 @@
2009-04-21 Richard Guenther <rguenther@suse.de>
PR tree-optimization/39827
* tree-ssa-phiprop.c (propagate_with_phi): Check SSA_NAME
is in range.
* tree-ssa-phiprop.c (propagate_with_phi): Check SSA_NAME is in range.
(tree_ssa_phiprop): Pass the correct array size.
2009-04-21 Uros Bizjak <ubizjak@gmail.com>
......
gcc/config/alpha/alpha.h
......@@ -447,7 +447,7 @@ extern enum alpha_fp_trap_mode alpha_fptm;
registers can hold 64-bit integers as well, but not smaller values. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) >= 32 && (REGNO) <= 62 \
(IN_RANGE ((REGNO), 32, 62) \
? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \
|| (MODE) == SCmode || (MODE) == DCmode \
: 1)
......@@ -576,7 +576,7 @@ enum reg_class {
: (REGNO) == 24 ? R24_REG \
: (REGNO) == 25 ? R25_REG \
: (REGNO) == 27 ? R27_REG \
: (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
: IN_RANGE ((REGNO), 32, 62) ? FLOAT_REGS \
: GENERAL_REGS)
/* The class value for index registers, and the one for base regs. */
......@@ -752,7 +752,7 @@ extern int alpha_memory_latency;
On Alpha, these are $16-$21 and $f16-$f21. */
#define FUNCTION_ARG_REGNO_P(N) \
(((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
(IN_RANGE ((N), 16, 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
......@@ -949,7 +949,7 @@ do { \
symbolic addresses into registers. */
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == CONST_INT \
(CONST_INT_P (X) \
&& (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
/* Include all constant integers and constant doubles, but not
......@@ -1125,7 +1125,7 @@ do { \
#define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
do { \
if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
&& (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
&& (REG_P (OP1) || (OP1) == const0_rtx)) \
{ \
rtx tem = (OP0); \
(OP0) = (OP1); \
......@@ -1133,7 +1133,7 @@ do { \
(CODE) = swap_condition (CODE); \
} \
if (((CODE) == LT || (CODE) == LTU) \
&& GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
&& CONST_INT_P (OP1) && INTVAL (OP1) == 256) \
{ \
(CODE) = (CODE) == LT ? LE : LEU; \
(OP1) = GEN_INT (255); \
......
gcc/config/alpha/alpha.md
......@@ -2155,7 +2155,7 @@
(match_operand:DI 2 "mul8_operand" "I"))
(match_operand:DI 3 "immediate_operand" "i")))]
"HOST_BITS_PER_WIDE_INT == 64
&& GET_CODE (operands[3]) == CONST_INT
&& CONST_INT_P (operands[3])
&& (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|| ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
......@@ -4249,11 +4249,11 @@
register since that is more likely to match (and to produce better code
if both would). */
if (code == EQ && GET_CODE (operands[3]) == CONST_INT
if (code == EQ && CONST_INT_P (operands[3])
&& rtx_equal_p (operands[4], operands[3]))
operands[4] = operands[2];
else if (code == NE && GET_CODE (operands[3]) == CONST_INT
else if (code == NE && CONST_INT_P (operands[3])
&& rtx_equal_p (operands[5], operands[3]))
operands[5] = operands[2];
......@@ -4261,7 +4261,7 @@
|| (extended_count (operands[2], DImode, unsignedp) >= 1
&& extended_count (operands[3], DImode, unsignedp) >= 1))
{
if (GET_CODE (operands[3]) == CONST_INT)
if (CONST_INT_P (operands[3]))
operands[7] = gen_rtx_PLUS (DImode, operands[2],
GEN_INT (- INTVAL (operands[3])));
else
......@@ -4308,7 +4308,7 @@
&& extended_count (operands[3], DImode, unsignedp) >= 1)))
FAIL;
if (GET_CODE (operands[3]) == CONST_INT)
if (CONST_INT_P (operands[3]))
tem = gen_rtx_PLUS (SImode, operands[2],
GEN_INT (- INTVAL (operands[3])));
else
......@@ -4547,7 +4547,7 @@
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
gcc_assert (GET_CODE (operands[0]) == MEM);
gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
})
......@@ -4558,7 +4558,7 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[0]) == MEM);
gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
if (! call_operand (operands[0], Pmode))
......@@ -4571,10 +4571,10 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[0]) == MEM);
gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
if (GET_CODE (operands[0]) != SYMBOL_REF && !REG_P (operands[0]))
operands[0] = force_reg (DImode, operands[0]);
})
......@@ -4589,13 +4589,13 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[0]) == MEM);
gcc_assert (MEM_P (operands[0]));
/* Always load the address of the called function into a register;
load the CIW in $25. */
operands[0] = XEXP (operands[0], 0);
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[0] = force_reg (DImode, operands[0]);
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
......@@ -4615,7 +4615,7 @@
(clobber (reg:DI 27))])]
""
{
gcc_assert (GET_CODE (operands[0]) == MEM);
gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
......@@ -4668,7 +4668,7 @@
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
gcc_assert (GET_CODE (operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
})
......@@ -4680,7 +4680,7 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
if (! call_operand (operands[1], Pmode))
......@@ -4694,10 +4694,10 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
if (GET_CODE (operands[1]) != SYMBOL_REF && !REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
})
......@@ -4711,7 +4711,7 @@
(clobber (reg:DI 27))])]
""
{
gcc_assert (GET_CODE (operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
......@@ -4742,10 +4742,10 @@
(clobber (reg:DI 26))])]
""
{
gcc_assert (GET_CODE (operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
if (GET_CODE (operands[1]) != REG)
if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
......@@ -5243,7 +5243,7 @@
(match_operand:SF 1 "general_operand" ""))]
""
{
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[1]);
})
......@@ -5253,7 +5253,7 @@
(match_operand:DF 1 "general_operand" ""))]
""
{
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[1]);
})
......@@ -5263,7 +5263,7 @@
(match_operand:TF 1 "general_operand" ""))]
""
{
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], TFmode))
operands[1] = force_reg (TFmode, operands[1]);
})
......@@ -5746,7 +5746,7 @@
(match_operand:TI 1 "general_operand" ""))]
""
{
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], TImode))
operands[1] = force_reg (TImode, operands[1]);
......@@ -5755,7 +5755,7 @@
/* We must put 64-bit constants in memory. We could keep the
32-bit constants in TImode and rely on the splitter, but
this doesn't seem to be worth the pain. */
else if (GET_CODE (operands[1]) == CONST_INT
else if (CONST_INT_P (operands[1])
|| GET_CODE (operands[1]) == CONST_DOUBLE)
{
rtx in[2], out[2], target;
......@@ -5780,7 +5780,7 @@
emit_insn (gen_movdi (out[1], in[1]));
}
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
target = gen_reg_rtx (TImode);
else
target = operands[0];
......@@ -6204,7 +6204,7 @@
rtx scratch3 = scratch1;
rtx seq;
if (GET_CODE (addr) == REG)
if (REG_P (addr))
scratch1 = addr;
seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
......@@ -6480,7 +6480,7 @@
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[1]) != MEM)
if (!MEM_P (operands[1]))
FAIL;
/* The bit number is relative to the mode of operand 1 which is
......@@ -6516,7 +6516,7 @@
&& INTVAL (operands[2]) != 64))
FAIL;
if (GET_CODE (operands[1]) == MEM)
if (MEM_P (operands[1]))
{
int ofs;
......@@ -6561,7 +6561,7 @@
/* From mips.md: store_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[0]) != MEM)
if (!MEM_P (operands[0]))
FAIL;
/* The bit number is relative to the mode of operand 1 which is
......@@ -6742,7 +6742,7 @@
(match_dup 2))]
""
{
if (GET_CODE (operands[1]) == CONST_INT
if (CONST_INT_P (operands[1])
&& INTVAL (operands[1]) < 32768)
{
if (INTVAL (operands[1]) >= 4096)
......@@ -6775,7 +6775,7 @@
force_reg (Pmode, operands[1])));
emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
if (GET_CODE (operands[1]) != CONST_INT)
if (!CONST_INT_P (operands[1]))
{
out_label = gen_label_rtx ();
emit_insn (gen_cmpdi (want, tmp));
......@@ -7533,7 +7533,7 @@
(match_operand:DI 1 "reg_or_cint_operand" "")))]
""
{
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
{
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
......@@ -7581,7 +7581,7 @@
[(const_int 0)]
{
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask))
operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
else
{
......@@ -7626,7 +7626,7 @@
(match_operand:DI 1 "reg_or_cint_operand" "")))]
""
{
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
{
rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
......
gcc/config/alpha/constraints.md
......@@ -42,7 +42,7 @@
(define_constraint "I"
"An unsigned 8 bit constant"
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 255")))
(match_test "IN_RANGE (ival, 0, 255)")))
(define_constraint "J"
"The constant zero"
......@@ -52,7 +52,7 @@
(define_constraint "K"
"Signed 16-bit integer constant"
(and (match_code "const_int")
(match_test "ival >= -32768 && ival < 32768 ")))
(match_test "IN_RANGE (ival, -32768, 32767)")))
(define_constraint "L"
"A shifted signed 16-bit constant appropriate for LDAH"
......@@ -68,12 +68,12 @@
(define_constraint "N"
"A complemented unsigned 8-bit constant"
(and (match_code "const_int")
(match_test "~ival >= 0 && ~ival <= 255")))
(match_test "IN_RANGE (~ival, 0, 255)")))
(define_constraint "O"
"A negated unsigned 8-bit constant"
(and (match_code "const_int")
(match_test "-ival >= 0 && -ival <= 255")))
(match_test "IN_RANGE (-ival, 0, 255)")))
(define_constraint "P"
"The constant 1, 2 or 3"
......@@ -104,7 +104,7 @@
(define_constraint "S"
"An unsigned 6-bit constant"
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 63")))
(match_test "IN_RANGE (ival, 0, 63)")))
(define_constraint "T"
"@internal A high-part symbol"
......
gcc/config/alpha/predicates.md
......@@ -112,7 +112,7 @@
(define_predicate "mode_mask_operand"
(match_code "const_int,const_double")
{
if (GET_CODE (op) == CONST_INT)
if (CONST_INT_P (op))
{
HOST_WIDE_INT value = INTVAL (op);
......@@ -326,7 +326,7 @@
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) == LABEL_REF)
......@@ -350,7 +350,7 @@
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) != SYMBOL_REF)
......@@ -374,7 +374,7 @@
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) != SYMBOL_REF)
......@@ -392,7 +392,7 @@
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
|| GET_CODE (XEXP (XEXP (op,0), 0)) == LABEL_REF)
&& GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT"))))
&& CONST_INT_P (XEXP (XEXP (op,0), 1))"))))
;; Return true if OP is valid for 16-bit DTP relative relocations.
(define_predicate "dtp16_symbolic_operand"
......@@ -457,7 +457,7 @@
base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
}
return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
return (REG_P (base) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
})
;; Similar, but return 1 if OP is a MEM which is not alignable.
......@@ -485,7 +485,7 @@
base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
}
return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
return (REG_P (base) && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
})
;; Return 1 if OP is any memory location. During reload a pseudo matches.
......
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