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Commit 7d20ca61 by Michael Meissner Committed by Michael Meissner
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re PR target/59054 (Powerpc -O0 -mcpu=power7 generates sub-optimal code to load 0) 

2013-11-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/59054
	* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
	specify an appropriate register class for VSX operations.
	(load_vsx): Use it.
	(load_gpr_to_vsx): Likewise.
	(load_vsx_to_gpr): Likewise.
	* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
	register class for VSX registers that the type can handle.  Remove
	checks for explicit number of instructions generated, just check
	if the instruction is generated.
	* gcc.target/powerpc/direct-move-vint2.c: Likewise.
	* gcc.target/powerpc/direct-move-float1.c: Likewise.
	* gcc.target/powerpc/direct-move-float2.c: Likewise.
	* gcc.target/powerpc/direct-move-double1.c: Likewise.
	* gcc.target/powerpc/direct-move-double2.c: Likewise.
	* gcc.target/powerpc/direct-move-long1.c: Likewise.
	* gcc.target/powerpc/direct-move-long2.c: Likewise.

	* gcc.target/powerpc/pr59054.c: Remove duplicate code.

	* gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
	* gcc.target/powerpc/bool3-p7.c: Likewise.
	* gcc.target/powerpc/bool3-p8.c: Likewise.

	* gcc.target/powerpc/p8vector-ldst.c: Just check that the
	appropriate instructions are generated, don't check the count.

From-SVN: r205278
parent 237c8b9d
Showing with 64 additions and 35 deletions
gcc/testsuite/ChangeLog
2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
specify an appropriate register class for VSX operations.
(load_vsx): Use it.
(load_gpr_to_vsx): Likewise.
(load_vsx_to_gpr): Likewise.
* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
register class for VSX registers that the type can handle. Remove
checks for explicit number of instructions generated, just check
if the instruction is generated.
* gcc.target/powerpc/direct-move-vint2.c: Likewise.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float2.c: Likewise.
* gcc.target/powerpc/direct-move-double1.c: Likewise.
* gcc.target/powerpc/direct-move-double2.c: Likewise.
* gcc.target/powerpc/direct-move-long1.c: Likewise.
* gcc.target/powerpc/direct-move-long2.c: Likewise.
* gcc.target/powerpc/pr59054.c: Remove duplicate code.
* gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
* gcc.target/powerpc/bool3-p7.c: Likewise.
* gcc.target/powerpc/bool3-p8.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Just check that the
appropriate instructions are generated, don't check the count.
2013-11-22 Richard Earnshaw <rearnsha@arm.com>
PR target/59216
......
gcc/testsuite/gcc.target/powerpc/bool3-av.c
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */
......
gcc/testsuite/gcc.target/powerpc/bool3-p7.c
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-O2 -mcpu=power7" } */
......
gcc/testsuite/gcc.target/powerpc/bool3-p8.c
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-O2 -mcpu=power8" } */
......
gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
......@@ -3,13 +3,14 @@
/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mcpu=power8 -O2" } */
/* { dg-final { scan-assembler-times "mtvsrd" 1 } } */
/* { dg-final { scan-assembler-times "mfvsrd" 1 } } */
/* { dg-final { scan-assembler "mtvsrd" } } */
/* { dg-final { scan-assembler "mfvsrd" } } */
/* Check code generation for direct move for long types. */
/* Check code generation for direct move for double types. */
#define TYPE double
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define VSX_REG_ATTR "ws"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
......@@ -10,5 +10,6 @@
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define DO_MAIN
#define VSX_REG_ATTR "ws"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
......@@ -3,15 +3,16 @@
/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mcpu=power8 -O2" } */
/* { dg-final { scan-assembler-times "mtvsrd" 2 } } */
/* { dg-final { scan-assembler-times "mfvsrd" 2 } } */
/* { dg-final { scan-assembler-times "xscvdpspn" 2 } } */
/* { dg-final { scan-assembler-times "xscvspdpn" 2 } } */
/* { dg-final { scan-assembler "mtvsrd" } } */
/* { dg-final { scan-assembler "mfvsrd" } } */
/* { dg-final { scan-assembler "xscvdpspn" } } */
/* { dg-final { scan-assembler "xscvspdpn" } } */
/* Check code generation for direct move for long types. */
/* Check code generation for direct move for float types. */
#define TYPE float
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define VSX_REG_ATTR "ww"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
......@@ -10,5 +10,6 @@
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define DO_MAIN
#define VSX_REG_ATTR "ww"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
......@@ -3,13 +3,14 @@
/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mcpu=power8 -O2" } */
/* { dg-final { scan-assembler-times "mtvsrd" 1 } } */
/* { dg-final { scan-assembler-times "mfvsrd" 2 } } */
/* { dg-final { scan-assembler "mtvsrd" } } */
/* { dg-final { scan-assembler "mfvsrd" } } */
/* Check code generation for direct move for long types. */
#define TYPE long
#define IS_INT 1
#define NO_ALTIVEC 1
#define VSX_REG_ATTR "d"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
......@@ -10,5 +10,6 @@
#define IS_INT 1
#define NO_ALTIVEC 1
#define DO_MAIN
#define VSX_REG_ATTR "d"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
......@@ -3,11 +3,12 @@
/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mcpu=power8 -O2" } */
/* { dg-final { scan-assembler-times "mtvsrd" 4 } } */
/* { dg-final { scan-assembler-times "mfvsrd" 4 } } */
/* { dg-final { scan-assembler "mtvsrd" } } */
/* { dg-final { scan-assembler "mfvsrd" } } */
/* Check code generation for direct move for long types. */
/* Check code generation for direct move for vector types. */
#define TYPE vector int
#define VSX_REG_ATTR "wa"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
......@@ -8,5 +8,6 @@
#define TYPE vector int
#define DO_MAIN
#define VSX_REG_ATTR "wa"
#include "direct-move.h"
gcc/testsuite/gcc.target/powerpc/direct-move.h
......@@ -3,6 +3,10 @@
#include <math.h>
extern void abort (void);
#ifndef VSX_REG_ATTR
#define VSX_REG_ATTR "wa"
#endif
void __attribute__((__noinline__))
copy (TYPE *a, TYPE *b)
{
......@@ -44,7 +48,7 @@ void __attribute__((__noinline__))
load_vsx (TYPE *a, TYPE *b)
{
TYPE c = *a;
__asm__ ("# vsx, reg = %x0" : "+wa" (c));
__asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
*b = c;
}
#endif
......@@ -57,7 +61,7 @@ load_gpr_to_vsx (TYPE *a, TYPE *b)
TYPE d;
__asm__ ("# gpr, reg = %0" : "+b" (c));
d = c;
__asm__ ("# vsx, reg = %x0" : "+wa" (d));
__asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));
*b = d;
}
#endif
......@@ -68,7 +72,7 @@ load_vsx_to_gpr (TYPE *a, TYPE *b)
{
TYPE c = *a;
TYPE d;
__asm__ ("# vsx, reg = %x0" : "+wa" (c));
__asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
d = c;
__asm__ ("# gpr, reg = %0" : "+b" (d));
*b = d;
......
gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
......@@ -36,7 +36,7 @@ void store_df (double *p, double d)
*p = d;
}
/* { dg-final { scan-assembler-times "lxsspx" 2 } } */
/* { dg-final { scan-assembler-times "lxsdx" 1 } } */
/* { dg-final { scan-assembler-times "stxsspx" 1 } } */
/* { dg-final { scan-assembler-times "stxsdx" 1 } } */
/* { dg-final { scan-assembler "lxsspx" } } */
/* { dg-final { scan-assembler "lxsdx" } } */
/* { dg-final { scan-assembler "stxsspx" } } */
/* { dg-final { scan-assembler "stxsdx" } } */
gcc/testsuite/gcc.target/powerpc/pr59054.c
......@@ -4,15 +4,3 @@
/* { dg-options "-mcpu=power7 -O0 -m64" } */
long foo (void) { return 0; }
/* { dg-final { scan-assembler-not "xxlor" } } */
/* { dg-final { scan-assembler-not "stfd" } } */
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mcpu=power7 -O0 -m64" } */
long foo (void) { return 0; }
/* { dg-final { scan-assembler-not "xxlor" } } */
/* { dg-final { scan-assembler-not "stfd" } } */
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