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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
7b64da89
Commit
7b64da89
authored
Dec 12, 1996
by
Richard Earnshaw
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(arm_gen_constant, case IOR,XOR): Don't invert a constant if loading
it into a temporary. From-SVN: r13290
parent
89418a92
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4 deletions
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gcc/config/arm/arm.c
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gcc/config/arm/arm.c
View file @
7b64da89
...
...
@@ -701,8 +701,8 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
case
IOR
:
case
XOR
:
/* If we have IOR or XOR, and the
inverse of the constant can be loaded
in a
single instruction, and we can find a temporary to put it in,
/* If we have IOR or XOR, and the
constant can be loaded in a
single instruction, and we can find a temporary to put it in,
then this can be done in two instructions instead of 3-4. */
if
(
subtargets
||
(
reload_completed
&&
!
reg_mentioned_p
(
target
,
source
)))
...
...
@@ -713,8 +713,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate)
{
rtx
sub
=
subtargets
?
gen_reg_rtx
(
mode
)
:
target
;
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
sub
,
GEN_INT
(
ARM_SIGN_EXTEND
(
~
val
))));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
sub
,
GEN_INT
(
val
)));
emit_insn
(
gen_rtx
(
SET
,
VOIDmode
,
target
,
gen_rtx
(
code
,
mode
,
source
,
sub
)));
}
...
...
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