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riscv-gcc-1
Commit 7b49c9e1 by James Greenhalgh Committed by James Greenhalgh
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[ARM,AARCH64] Insn type reclassification. Split f_cvt type. 

gcc/
	* config/arm/types.md
	(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
	* config/aarch64/aarch64.md
	(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
	new attributes.
	(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
	(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
	(float<GPI:mode><GPF:mode>2): Likewise.
	* config/arm/vfp.md
	(*truncsisf2_vfp): Update with new attributes.
	(*truncsidf2_vfp): Likewise.
	(fixuns_truncsfsi2): Likewise.
	(fixuns_truncdfsi2): Likewise.
	(*floatsisf2_vfp): Likewise.
	(*floatsidf2_vfp): Likewise.
	(floatunssisf2): Likewise.
	(floatunssidf2): Likewise.
	(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
	(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.

From-SVN: r202328
parent e7df8af8
Showing with 67 additions and 26 deletions
gcc/ChangeLog
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md
(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
* config/aarch64/aarch64.md
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
new attributes.
(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
(float<GPI:mode><GPF:mode>2): Likewise.
* config/arm/vfp.md
(*truncsisf2_vfp): Update with new attributes.
(*truncsidf2_vfp): Likewise.
(fixuns_truncsfsi2): Likewise.
(fixuns_truncdfsi2): Likewise.
(*floatsisf2_vfp): Likewise.
(*floatsidf2_vfp): Likewise.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/arm_neon.h * config/aarch64/arm_neon.h
(vqtbl<1,2,3,4><q>_s8): Fix control vector parameter type. (vqtbl<1,2,3,4><q>_s8): Fix control vector parameter type.
(vqtbx<1,2,3,4><q>_s8): Likewise. (vqtbx<1,2,3,4><q>_s8): Likewise.
......
gcc/config/aarch64/aarch64.md
...@@ -3685,7 +3685,7 @@ ...@@ -3685,7 +3685,7 @@
"TARGET_FLOAT" "TARGET_FLOAT"
"fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1" "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i") [(set_attr "v8type" "fcvtf2i")
(set_attr "type" "f_cvt") (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>") (set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")] (set_attr "mode2" "<GPI:MODE>")]
) )
...@@ -3785,7 +3785,7 @@ ...@@ -3785,7 +3785,7 @@
"TARGET_FLOAT" "TARGET_FLOAT"
"fcvtzs\\t%<GPI:w>0, %<GPF:s>1" "fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i") [(set_attr "v8type" "fcvtf2i")
(set_attr "type" "f_cvt") (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>") (set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")] (set_attr "mode2" "<GPI:MODE>")]
) )
...@@ -3796,7 +3796,7 @@ ...@@ -3796,7 +3796,7 @@
"TARGET_FLOAT" "TARGET_FLOAT"
"fcvtzu\\t%<GPI:w>0, %<GPF:s>1" "fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i") [(set_attr "v8type" "fcvtf2i")
(set_attr "type" "f_cvt") (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>") (set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")] (set_attr "mode2" "<GPI:MODE>")]
) )
...@@ -3807,7 +3807,7 @@ ...@@ -3807,7 +3807,7 @@
"TARGET_FLOAT" "TARGET_FLOAT"
"scvtf\\t%<GPF:s>0, %<GPI:w>1" "scvtf\\t%<GPF:s>0, %<GPI:w>1"
[(set_attr "v8type" "fcvti2f") [(set_attr "v8type" "fcvti2f")
(set_attr "type" "f_cvt") (set_attr "type" "f_cvti2f")
(set_attr "mode" "<GPF:MODE>") (set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")] (set_attr "mode2" "<GPI:MODE>")]
) )
......
gcc/config/arm/arm1020e.md
...@@ -289,7 +289,7 @@ ...@@ -289,7 +289,7 @@
(define_insn_reservation "v10_cvt" 5 (define_insn_reservation "v10_cvt" 5
(and (eq_attr "vfp10" "yes") (and (eq_attr "vfp10" "yes")
(eq_attr "type" "f_cvt")) (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
"1020a_e+v10_fmac") "1020a_e+v10_fmac")
(define_insn_reservation "v10_fmul" 6 (define_insn_reservation "v10_fmul" 6
......
gcc/config/arm/cortex-a15-neon.md
...@@ -471,7 +471,7 @@ ...@@ -471,7 +471,7 @@
(define_insn_reservation "cortex_a15_vfp_cvt" 6 (define_insn_reservation "cortex_a15_vfp_cvt" 6
(and (eq_attr "tune" "cortexa15") (and (eq_attr "tune" "cortexa15")
(eq_attr "type" "f_cvt")) (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"ca15_issue1,ca15_cx_vfp") "ca15_issue1,ca15_cx_vfp")
(define_insn_reservation "cortex_a15_vfp_cmpd" 8 (define_insn_reservation "cortex_a15_vfp_cmpd" 8
......
gcc/config/arm/cortex-a5.md
...@@ -168,7 +168,8 @@ ...@@ -168,7 +168,8 @@
(define_insn_reservation "cortex_a5_fpalu" 4 (define_insn_reservation "cortex_a5_fpalu" 4
(and (eq_attr "tune" "cortexa5") (and (eq_attr "tune" "cortexa5")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd")) fcmps, fcmpd"))
"cortex_a5_ex1+cortex_a5_fpadd_pipe") "cortex_a5_ex1+cortex_a5_fpadd_pipe")
......
gcc/config/arm/cortex-a53.md
...@@ -209,7 +209,8 @@ ...@@ -209,7 +209,8 @@
(define_insn_reservation "cortex_a53_fpalu" 4 (define_insn_reservation "cortex_a53_fpalu" 4
(and (eq_attr "tune" "cortexa53") (and (eq_attr "tune" "cortexa53")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd, fcsel")) fcmps, fcmpd, fcsel"))
"cortex_a53_slot0+cortex_a53_fpadd_pipe") "cortex_a53_slot0+cortex_a53_fpadd_pipe")
......
gcc/config/arm/cortex-a7.md
...@@ -205,7 +205,7 @@ ...@@ -205,7 +205,7 @@
(define_insn_reservation "cortex_a7_fpalu" 4 (define_insn_reservation "cortex_a7_fpalu" 4
(and (eq_attr "tune" "cortexa7") (and (eq_attr "tune" "cortexa7")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
f_cvt, fcmps, fcmpd")) f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe") "cortex_a7_ex1+cortex_a7_fpadd_pipe")
;; For fconsts and fconstd, 8-bit immediate data is passed directly from ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
......
gcc/config/arm/cortex-a8-neon.md
...@@ -177,7 +177,7 @@ ...@@ -177,7 +177,7 @@
(define_insn_reservation "cortex_a8_vfp_cvt" 7 (define_insn_reservation "cortex_a8_vfp_cvt" 7
(and (eq_attr "tune" "cortexa8") (and (eq_attr "tune" "cortexa8")
(eq_attr "type" "f_cvt")) (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_a8_vfp,cortex_a8_vfplite*6") "cortex_a8_vfp,cortex_a8_vfplite*6")
;; NEON -> core transfers. ;; NEON -> core transfers.
......
gcc/config/arm/cortex-a9.md
...@@ -233,7 +233,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") ...@@ -233,7 +233,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
(define_insn_reservation "cortex_a9_fadd" 4 (define_insn_reservation "cortex_a9_fadd" 4
(and (eq_attr "tune" "cortexa9") (and (eq_attr "tune" "cortexa9")
(eq_attr "type" "fadds, faddd, f_cvt")) (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f"))
"ca9fp_add") "ca9fp_add")
(define_insn_reservation "cortex_a9_fcmp" 1 (define_insn_reservation "cortex_a9_fcmp" 1
......
gcc/config/arm/cortex-m4-fpu.md
...@@ -77,7 +77,7 @@ ...@@ -77,7 +77,7 @@
(define_insn_reservation "cortex_m4_f_cvt" 2 (define_insn_reservation "cortex_m4_f_cvt" 2
(and (eq_attr "tune" "cortexm4") (and (eq_attr "tune" "cortexm4")
(eq_attr "type" "f_cvt")) (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_m4_ex_v") "cortex_m4_ex_v")
(define_insn_reservation "cortex_m4_f_load" 2 (define_insn_reservation "cortex_m4_f_load" 2
......
gcc/config/arm/cortex-r4f.md
...@@ -146,7 +146,7 @@ ...@@ -146,7 +146,7 @@
(define_insn_reservation "cortex_r4_f_cvt" 8 (define_insn_reservation "cortex_r4_f_cvt" 8
(and (eq_attr "tune_cortexr4" "yes") (and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "f_cvt")) (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_r4_single_issue*3") "cortex_r4_single_issue*3")
(define_insn_reservation "cortex_r4_f_memd" 8 (define_insn_reservation "cortex_r4_f_memd" 8
......
gcc/config/arm/marvell-pj4.md
...@@ -209,7 +209,8 @@ ...@@ -209,7 +209,8 @@
(define_insn_reservation "pj4_vfp_cpy" 4 (define_insn_reservation "pj4_vfp_cpy" 4
(and (eq_attr "tune" "marvell_pj4") (and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\ (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfast,nothing*2") fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
"pj4_is,nothing*2,vissue,vfast,nothing*2")
;; Enlarge latency, and wish that more nondependent insns are ;; Enlarge latency, and wish that more nondependent insns are
;; scheduled immediately after VFP load. ;; scheduled immediately after VFP load.
......
gcc/config/arm/types.md
...@@ -55,7 +55,9 @@ ...@@ -55,7 +55,9 @@
; clz count leading zeros (CLZ). ; clz count leading zeros (CLZ).
; csel From ARMv8-A: conditional select. ; csel From ARMv8-A: conditional select.
; extend extend instruction (SXTB, SXTH, UXTB, UXTH). ; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_cvt conversion between float and integral. ; f_cvt conversion between float representations.
; f_cvtf2i conversion between float and integral types.
; f_cvti2f conversion between integral and float types.
; f_flag transfer of co-processor flags to the CPSR. ; f_flag transfer of co-processor flags to the CPSR.
; f_load[d,s] double/single load from memory. Used for VFP unit. ; f_load[d,s] double/single load from memory. Used for VFP unit.
; f_mcr transfer arm to vfp reg. ; f_mcr transfer arm to vfp reg.
...@@ -311,6 +313,8 @@ ...@@ -311,6 +313,8 @@
csel,\ csel,\
extend,\ extend,\
f_cvt,\ f_cvt,\
f_cvtf2i,\
f_cvti2f,\
f_flag,\ f_flag,\
f_loadd,\ f_loadd,\
f_loads,\ f_loads,\
......
gcc/config/arm/vfp.md
...@@ -991,7 +991,7 @@ ...@@ -991,7 +991,7 @@
"ftosizs%?\\t%0, %1" "ftosizs%?\\t%0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvtf2i")]
) )
(define_insn "*truncsidf2_vfp" (define_insn "*truncsidf2_vfp"
...@@ -1001,7 +1001,7 @@ ...@@ -1001,7 +1001,7 @@
"ftosizd%?\\t%0, %P1" "ftosizd%?\\t%0, %P1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvtf2i")]
) )
...@@ -1012,7 +1012,7 @@ ...@@ -1012,7 +1012,7 @@
"ftouizs%?\\t%0, %1" "ftouizs%?\\t%0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvtf2i")]
) )
(define_insn "fixuns_truncdfsi2" (define_insn "fixuns_truncdfsi2"
...@@ -1022,7 +1022,7 @@ ...@@ -1022,7 +1022,7 @@
"ftouizd%?\\t%0, %P1" "ftouizd%?\\t%0, %P1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvtf2i")]
) )
...@@ -1033,7 +1033,7 @@ ...@@ -1033,7 +1033,7 @@
"fsitos%?\\t%0, %1" "fsitos%?\\t%0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvti2f")]
) )
(define_insn "*floatsidf2_vfp" (define_insn "*floatsidf2_vfp"
...@@ -1043,7 +1043,7 @@ ...@@ -1043,7 +1043,7 @@
"fsitod%?\\t%P0, %1" "fsitod%?\\t%P0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvti2f")]
) )
...@@ -1054,7 +1054,7 @@ ...@@ -1054,7 +1054,7 @@
"fuitos%?\\t%0, %1" "fuitos%?\\t%0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvti2f")]
) )
(define_insn "floatunssidf2" (define_insn "floatunssidf2"
...@@ -1064,7 +1064,7 @@ ...@@ -1064,7 +1064,7 @@
"fuitod%?\\t%P0, %1" "fuitod%?\\t%P0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvti2f")]
) )
...@@ -1229,7 +1229,7 @@ ...@@ -1229,7 +1229,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2" "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
[(set_attr "predicable" "no") [(set_attr "predicable" "no")
(set_attr "type" "f_cvt")] (set_attr "type" "f_cvti2f")]
) )
;; Not the ideal way of implementing this. Ideally we would be able to split ;; Not the ideal way of implementing this. Ideally we would be able to split
...@@ -1246,7 +1246,7 @@ ...@@ -1246,7 +1246,7 @@
vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2 vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2" vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
[(set_attr "predicable" "no") [(set_attr "predicable" "no")
(set_attr "type" "f_cvt") (set_attr "type" "f_cvti2f")
(set_attr "length" "8")] (set_attr "length" "8")]
) )
......
gcc/config/arm/vfp11.md
...@@ -56,7 +56,8 @@ ...@@ -56,7 +56,8 @@
(define_insn_reservation "vfp_farith" 8 (define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes") (and (eq_attr "generic_vfp" "yes")
(eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas")) (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
fmuls,fmacs,ffmas"))
"fmac") "fmac")
(define_insn_reservation "vfp_fmul" 9 (define_insn_reservation "vfp_fmul" 9
......
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