Commit 7b3d1847 by Uros Bizjak

sync.md: Update comment about unpredictable LL/SC lock clearing by a taken branch.

	* config/alpha/sync.md: Update comment about unpredictable LL/SC lock
	clearing by a taken branch.
	(sync_<fetchop_name><mode>): Split when epilogue_completed is set,
	effectively after bbro pass.
	(sync_nand<mode>): Ditto.
	(sync_old_<fetchop_name><mode>): Ditto.
	(sync_old_nand<mode>): Ditto.
	(sync_new_<fetchop_name><mode>): Dito.
	(sync_new_nand<mode>): Ditto.
	(sync_compare_and_swap<mode>_1): Ditto.
	(*sync_compare_and_swap<mode>): Ditto.
	(sync_lock_test_and_set<mode>_1): Ditto.
	("sync_lock_test_and_set<mode>): Ditto.

From-SVN: r151115
parent 1dad57e6
2009-08-26 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/sync.md: Update comment about unpredictable LL/SC lock
clearing by a taken branch.
(sync_<fetchop_name><mode>): Split when epilogue_completed is set,
effectively after bbro pass.
(sync_nand<mode>): Ditto.
(sync_old_<fetchop_name><mode>): Ditto.
(sync_old_nand<mode>): Ditto.
(sync_new_<fetchop_name><mode>): Dito.
(sync_new_nand<mode>): Ditto.
(sync_compare_and_swap<mode>_1): Ditto.
(*sync_compare_and_swap<mode>): Ditto.
(sync_lock_test_and_set<mode>_1): Ditto.
("sync_lock_test_and_set<mode>): Ditto.
2009-08-25 Douglas B Rupp <rupp@gnat.com> 2009-08-25 Douglas B Rupp <rupp@gnat.com>
* hwint.h (HOST_LONG_FORMAT): New macro * hwint.h (HOST_LONG_FORMAT): New macro
...@@ -406,9 +422,10 @@ ...@@ -406,9 +422,10 @@
(sse5_maskcmp_uns<mode>3): Ditto. (sse5_maskcmp_uns<mode>3): Ditto.
(sse5_maskcmp_uns2<mode>3): Ditto. (sse5_maskcmp_uns2<mode>3): Ditto.
(sse5_pcom_tf<mode>3): Ditto. (sse5_pcom_tf<mode>3): Ditto.
* config/i386/predicates.md (sse5_comparison_float_operator): New predicate to match the * config/i386/predicates.md (sse5_comparison_float_operator):
comparison operators supported by the SSE5 com instruction. New predicate to match the comparison operators supported by
the SSE5 com instruction.
(ix86_comparison_int_operator): New predicate to match just the (ix86_comparison_int_operator): New predicate to match just the
signed int comparisons. signed int comparisons.
(ix86_comparison_uns_operator): New predicate to match just the (ix86_comparison_uns_operator): New predicate to match just the
...@@ -484,7 +501,7 @@ ...@@ -484,7 +501,7 @@
* config/crx/crx.h (CAN_ELIMINATE): Remove macro. * config/crx/crx.h (CAN_ELIMINATE): Remove macro.
* config/crx/crx.c (TARGET_CAN_ELIMINATE): Define macro. * config/crx/crx.c (TARGET_CAN_ELIMINATE): Define macro.
(crx_can_eliminate): New function. (crx_can_eliminate): New function.
* config/fr30/fr30.h (CAN_ELIMINATE): Remove macro. * config/fr30/fr30.h (CAN_ELIMINATE): Remove macro.
* config/fr30/fr30.c (TARGET_CAN_ELIMINATE): Define macro. * config/fr30/fr30.c (TARGET_CAN_ELIMINATE): Define macro.
(fr30_can_eliminate): New function. (fr30_can_eliminate): New function.
...@@ -649,23 +666,23 @@ ...@@ -649,23 +666,23 @@
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (output_return_instruction): Handle for * config/arm/arm.c (output_return_instruction): Handle for
unified syntax. unified syntax.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_select_cc_mode): Handle subreg. * config/arm/arm.c (arm_select_cc_mode): Handle subreg.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable. * config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable.
(*arm_movdf_vfp): Likewise. (*arm_movdf_vfp): Likewise.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/neon.md (vashl<mode>3): Rename from ashl<mode>3. * config/arm/neon.md (vashl<mode>3): Rename from ashl<mode>3.
(vashr<mode>3): Rename from ashr<mode>3. (vashr<mode>3): Rename from ashr<mode>3.
(vlshr<mode>3): Rename from lshr<mode>3. (vlshr<mode>3): Rename from lshr<mode>3.
2009-08-24 Kai Tietz <kai.tietz@onevision.com> 2009-08-24 Kai Tietz <kai.tietz@onevision.com>
......
...@@ -62,11 +62,8 @@ ...@@ -62,11 +62,8 @@
[(set_attr "type" "st_c")]) [(set_attr "type" "st_c")])
;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether ;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
;; the lock is cleared by a TAKEN branch. If we were to honor that, it ;; the lock is cleared by a TAKEN branch. This means that we can not
;; would mean that we could not expand a ll/sc sequence until after the ;; expand a ll/sc sequence until after the final basic-block reordering pass.
;; final basic-block reordering pass. Fortunately, it appears that no
;; Alpha implementation ever built actually clears the lock on branches,
;; taken or not.
(define_insn_and_split "sync_<fetchop_name><mode>" (define_insn_and_split "sync_<fetchop_name><mode>"
[(set (match_operand:I48MODE 0 "memory_operand" "+m") [(set (match_operand:I48MODE 0 "memory_operand" "+m")
...@@ -77,7 +74,7 @@ ...@@ -77,7 +74,7 @@
(clobber (match_scratch:I48MODE 2 "=&r"))] (clobber (match_scratch:I48MODE 2 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (<CODE>, operands[0], operands[1], alpha_split_atomic_op (<CODE>, operands[0], operands[1],
...@@ -96,7 +93,7 @@ ...@@ -96,7 +93,7 @@
(clobber (match_scratch:I48MODE 2 "=&r"))] (clobber (match_scratch:I48MODE 2 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (NOT, operands[0], operands[1], alpha_split_atomic_op (NOT, operands[0], operands[1],
...@@ -116,7 +113,7 @@ ...@@ -116,7 +113,7 @@
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (<CODE>, operands[1], operands[2], alpha_split_atomic_op (<CODE>, operands[1], operands[2],
...@@ -137,7 +134,7 @@ ...@@ -137,7 +134,7 @@
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (NOT, operands[1], operands[2], alpha_split_atomic_op (NOT, operands[1], operands[2],
...@@ -158,7 +155,7 @@ ...@@ -158,7 +155,7 @@
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (<CODE>, operands[1], operands[2], alpha_split_atomic_op (<CODE>, operands[1], operands[2],
...@@ -179,7 +176,7 @@ ...@@ -179,7 +176,7 @@
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_atomic_op (NOT, operands[1], operands[2], alpha_split_atomic_op (NOT, operands[1], operands[2],
...@@ -214,7 +211,7 @@ ...@@ -214,7 +211,7 @@
(clobber (match_scratch:DI 6 "=X,&r"))] (clobber (match_scratch:DI 6 "=X,&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1], alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],
...@@ -251,7 +248,7 @@ ...@@ -251,7 +248,7 @@
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_compare_and_swap (operands[0], operands[1], operands[2], alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
...@@ -282,7 +279,7 @@ ...@@ -282,7 +279,7 @@
(clobber (match_scratch:DI 4 "=&r"))] (clobber (match_scratch:DI 4 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1], alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],
...@@ -301,7 +298,7 @@ ...@@ -301,7 +298,7 @@
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
"#" "#"
"reload_completed" "epilogue_completed"
[(const_int 0)] [(const_int 0)]
{ {
alpha_split_lock_test_and_set (operands[0], operands[1], alpha_split_lock_test_and_set (operands[0], operands[1],
......
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