Commit 7b37ce10 by Jakub Jelinek Committed by Jakub Jelinek

sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use constraint x instead of v…

sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use constraint x instead of v in second alternative, add avx512bw alternative.

	* config/i386/sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use
	constraint x instead of v in second alternative, add avx512bw
	alternative.

	* gcc.target/i386/avx512vl-vpmulhrsw-3.c: New test.
	* gcc.target/i386/avx512bw-vpmulhrsw-3.c: New test.

From-SVN: r236366
parent fb7cbdeb
2016-05-18 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use
constraint x instead of v in second alternative, add avx512bw
alternative.
* config/i386/sse.md (avx2_pmaddubsw256, ssse3_pmaddubsw128): Add
avx512bw alternative.
......
......@@ -14170,16 +14170,16 @@
})
(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x,v")
(truncate:VI2_AVX2
(lshiftrt:<ssedoublemode>
(plus:<ssedoublemode>
(lshiftrt:<ssedoublemode>
(mult:<ssedoublemode>
(sign_extend:<ssedoublemode>
(match_operand:VI2_AVX2 1 "vector_operand" "%0,v"))
(match_operand:VI2_AVX2 1 "vector_operand" "%0,x,v"))
(sign_extend:<ssedoublemode>
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,xm,vm")))
(const_int 14))
(match_operand:VI2_AVX2 3 "const1_operand"))
(const_int 1))))]
......@@ -14187,12 +14187,13 @@
&& ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
"@
pmulhrsw\t{%2, %0|%0, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
[(set_attr "isa" "noavx,avx")
[(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseimul")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*ssse3_pmulhrswv4hi3"
......
2016-05-18 Jakub Jelinek <jakub@redhat.com>
* gcc.target/i386/avx512vl-vpmulhrsw-3.c: New test.
* gcc.target/i386/avx512bw-vpmulhrsw-3.c: New test.
* gcc.target/i386/avx512bw-vpmaddubsw-3.c: New test.
2016-05-18 Richard Biener <rguenther@suse.de>
......
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
#include <x86intrin.h>
void
f1 (__m128i x, __m128i y)
{
register __m128i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm_mulhrs_epi16 (a, b);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler "vpmulhrsw\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */
void
f2 (__m256i x, __m256i y)
{
register __m256i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm256_mulhrs_epi16 (a, b);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler "vpmulhrsw\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
#include <x86intrin.h>
void
f1 (__m128i x, __m128i y)
{
register __m128i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm_mulhrs_epi16 (a, b);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler-not "vpmulhrsw\[^\n\r]*xmm1\[67]" } } */
void
f2 (__m256i x, __m256i y)
{
register __m256i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm256_mulhrs_epi16 (a, b);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler-not "vpmulhrsw\[^\n\r]*ymm1\[67]" } } */
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