sparc.c (gen_df_reg): New function.

	* config/sparc/sparc.c (gen_df_reg): New function.
	* config/sparc/sparc-protos.h (gen_df_reg): Add prototype.
	* config/sparc/sparc.md (movtf_no_e_insn_sp64+1,
	movtf_no_e_insn_sp64+2, movtf_no_e_insn_sp64+3, movtf_cc_sp64+1,
	movtf_cc_reg_sp64+1): Use it.

From-SVN: r31177

gcc/ChangeLog

+2000-01-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/sparc/sparc.c (gen_df_reg): New function.
+	* config/sparc/sparc-protos.h (gen_df_reg): Add prototype.
+	* config/sparc/sparc.md (movtf_no_e_insn_sp64+1,
+	movtf_no_e_insn_sp64+2, movtf_no_e_insn_sp64+3, movtf_cc_sp64+1,
+	movtf_cc_reg_sp64+1): Use it.
+
 2000-01-02  Mark Mitchell  <mark@codesourcery.com>
 
 	* integrate.c (copy_decl_for_inlining): Clear TREE_ADDRESSABLE on

gcc/config/sparc/sparc-protos.h

@@ -162,6 +162,7 @@ extern int eq_or_neq PARAMS ((rtx, enum machine_mode));
 extern int normal_comp_operator PARAMS ((rtx, enum machine_mode));
 extern int uns_arith_operand PARAMS ((rtx, enum machine_mode));
 extern int clobbered_register PARAMS ((rtx, enum machine_mode));
+extern rtx gen_df_reg PARAMS ((rtx, int));
 #endif /* RTX_CODE */
 
 #endif /* __SPARC_PROTOS_H__ */

gcc/config/sparc/sparc.c

@@ -2264,6 +2264,22 @@ emit_v9_brxx_insn (code, op0, label)
 				    gen_rtx_LABEL_REF (VOIDmode, label),
 				    pc_rtx)));
 }
+
+/* Generate a DFmode part of a hard TFmode register.
+   REG is the TFmode hard register, LOW is 1 for the
+   low 64bit of the register and 0 otherwise.
+ */
+rtx
+gen_df_reg (reg, low)
+     rtx reg;
+     int low;
+{
+  int regno = REGNO (reg);
+
+  if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
+    regno += (regno < 32) ? 1 : 2;
+  return gen_rtx_REG (DFmode, regno);
+}
 
 /* Return nonzero if a return peephole merging return with
    setting of output register is ok.  */

gcc/config/sparc/sparc.md

@@ -3643,14 +3643,10 @@
   if (GET_CODE (set_src) == SUBREG)
     set_src = alter_subreg (set_src);
 
-  dest1 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  dest2 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  src1 = gen_rtx_REG (DFmode,
-                      REGNO (set_src) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  src2 = gen_rtx_REG (DFmode,
-                      REGNO (set_src) + (WORDS_BIG_ENDIAN ? 2 : 0));
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  src1 = gen_df_reg (set_src, 0);
+  src2 = gen_df_reg (set_src, 1);
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */
@@ -3684,10 +3680,8 @@
   if (GET_CODE (set_dest) == SUBREG)
     set_dest = alter_subreg (set_dest);
 
-  dest1 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  dest2 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
 
   /* Now output, ordering such that we don't clobber any registers
      mentioned in the address.  */
@@ -3716,18 +3710,14 @@
   rtx word1 = change_address (operands[0], DFmode, NULL_RTX);
   rtx word2 = change_address (operands[0], DFmode,
 			      plus_constant_for_output (XEXP (word1, 0), 8));
-  rtx set_src, src1, src2;
+  rtx set_src;
 
   set_src = operands[1];
   if (GET_CODE (set_src) == SUBREG)
     set_src = alter_subreg (set_src);
 
-  src1 = gen_rtx_REG (DFmode,
-                      REGNO (set_src) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  src2 = gen_rtx_REG (DFmode,
-                      REGNO (set_src) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  emit_insn (gen_movdf (word1, src1));
-  emit_insn (gen_movdf (word2, src2));
+  emit_insn (gen_movdf (word1, gen_df_reg (set_src, 0)));
+  emit_insn (gen_movdf (word2, gen_df_reg (set_src, 1)));
   DONE;
 }")
 
@@ -4095,18 +4085,12 @@
   if (GET_CODE (set_srcb) == SUBREG)
     set_srcb = alter_subreg (set_srcb);
 
-  dest1 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  dest2 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  srca1 = gen_rtx_REG (DFmode,
-                       REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  srca2 = gen_rtx_REG (DFmode,
-                       REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  srcb1 = gen_rtx_REG (DFmode,
-                       REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  srcb2 = gen_rtx_REG (DFmode,
-                       REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 2 : 0));
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  srca1 = gen_df_reg (set_srca, 0);
+  srca2 = gen_df_reg (set_srca, 1);
+  srcb1 = gen_df_reg (set_srcb, 0);
+  srcb2 = gen_df_reg (set_srcb, 1);
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */
@@ -4274,18 +4258,12 @@
   if (GET_CODE (set_srcb) == SUBREG)
     set_srcb = alter_subreg (set_srcb);
 
-  dest1 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  dest2 = gen_rtx_REG (DFmode,
-                       REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  srca1 = gen_rtx_REG (DFmode,
-                       REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  srca2 = gen_rtx_REG (DFmode,
-                       REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 2 : 0));
-  srcb1 = gen_rtx_REG (DFmode,
-                       REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 0 : 2));
-  srcb2 = gen_rtx_REG (DFmode,
-                       REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 2 : 0));
+  dest1 = gen_df_reg (set_dest, 0);
+  dest2 = gen_df_reg (set_dest, 1);
+  srca1 = gen_df_reg (set_srca, 0);
+  srca2 = gen_df_reg (set_srca, 1);
+  srcb1 = gen_df_reg (set_srcb, 0);
+  srcb2 = gen_df_reg (set_srcb, 1);
 
   /* Now emit using the real source and destination we found, swapping
      the order if we detect overlap.  */