MAINTAINERS: Add myself as mep maintainer.

[toplevel]

	* MAINTAINERS: Add myself as mep maintainer.

[gcc]

	Add MeP port.
	* config.gcc: Add mep support.
	* recog.c: Resurrect validate_replace_rtx_subexp().
	* recog.h: Likewise.
	* config/mep/: Add new port:
	* config/mep/constraints.md: New file.
	* config/mep/default.h: New file.
	* config/mep/intrinsics.h: New file.
	* config/mep/intrinsics.md: New file.
	* config/mep/ivc2-template.h: New file.
	* config/mep/mep-c5.cpu: New file.
	* config/mep/mep-core.cpu: New file.
	* config/mep/mep-default.cpu: New file.
	* config/mep/mep-ext-cop.cpu: New file.
	* config/mep/mep-intrin.h: New file.
	* config/mep/mep-ivc2.cpu: New file.
	* config/mep/mep-lib1.asm: New file.
	* config/mep/mep-lib2.c: New file.
	* config/mep/mep-pragma.c: New file.
	* config/mep/mep-protos.h: New file.
	* config/mep/mep-tramp.c: New file.
	* config/mep/mep.c: New file.
	* config/mep/mep.cpu: New file.
	* config/mep/mep.h: New file.
	* config/mep/mep.md: New file.
	* config/mep/mep.opt: New file.
	* config/mep/predicates.md: New file.
	* config/mep/t-mep: New file.

[gcc/testsuite]

	Add MeP port.
	* lib/target-supports.exp: Add mep support (no profiling).

[libgcc]

	Add MeP port.
	* config.host: Add mep support.

[libstdc++-v3]

	Add MeP port.
	* configure.host: Add mep support.

From-SVN: r148890

ChangeLog

+2009-06-23  DJ Delorie  <dj@redhat.com>
+
+	* MAINTAINERS: Add myself as mep maintainer.
+
 2009-06-23  Ian Lance Taylor  <iant@google.com>
 
 	* configure.ac: Add --enable-build-with-cxx.  When set, add c++ to

MAINTAINERS

@@ -69,6 +69,7 @@ m68k port (?)		Jeff Law		law@redhat.com
 m68k port		Andreas Schwab		schwab@linux-m68k.org
 m68k-motorola-sysv port	Philippe De Muyter	phdm@macqel.be
 mcore port		Nick Clifton		nickc@redhat.com
+mep port		DJ Delorie		dj@redhat.com
 mips port		Eric Christopher	echristo@apple.com
 mips port		Richard Sandiford	rdsandiford@googlemail.com
 mmix port		Hans-Peter Nilsson	hp@bitrange.com

gcc/ChangeLog

+2009-06-23  DJ Delorie  <dj@redhat.com>
+
+	Add MeP port.
+	* config.gcc: Add mep support.
+	* recog.c: Resurrect validate_replace_rtx_subexp().
+	* recog.h: Likewise.
+	* config/mep/: Add new port:
+	* config/mep/constraints.md: New file.
+	* config/mep/default.h: New file.
+	* config/mep/intrinsics.h: New file.
+	* config/mep/intrinsics.md: New file.
+	* config/mep/ivc2-template.h: New file.
+	* config/mep/mep-c5.cpu: New file.
+	* config/mep/mep-core.cpu: New file.
+	* config/mep/mep-default.cpu: New file.
+	* config/mep/mep-ext-cop.cpu: New file.
+	* config/mep/mep-intrin.h: New file.
+	* config/mep/mep-ivc2.cpu: New file.
+	* config/mep/mep-lib1.asm: New file.
+	* config/mep/mep-lib2.c: New file.
+	* config/mep/mep-pragma.c: New file.
+	* config/mep/mep-protos.h: New file.
+	* config/mep/mep-tramp.c: New file.
+	* config/mep/mep.c: New file.
+	* config/mep/mep.cpu: New file.
+	* config/mep/mep.h: New file.
+	* config/mep/mep.md: New file.
+	* config/mep/mep.opt: New file.
+	* config/mep/predicates.md: New file.
+	* config/mep/t-mep: New file.
+
 2009-06-23  Ian Lance Taylor  <iant@google.com>
 
 	* configure.ac: Invoke AC_PROG_CXX.  Separate C specific warnings

gcc/config.gcc

@@ -1562,6 +1562,18 @@ mcore-*-pe*)
 	inhibit_libc=true
 	use_gcc_stdint=wrap
 	;;
+mep-*-*)
+	tm_file="dbxelf.h elfos.h svr4.h ${tm_file}"
+	tmake_file=mep/t-mep
+	extra_parts="crtbegin.o crtend.o"
+	c_target_objs="mep-pragma.o"
+	cxx_target_objs="mep-pragma.o"
+	if test -d "${srcdir}/../newlib/libc/include" &&
+	   test "x$with_headers" = x; then
+		with_headers=yes
+	fi
+	use_gcc_stdint=wrap
+	;;
 mips-sgi-irix[56]*)
 	tm_file="elfos.h ${tm_file} mips/iris.h"
 	tmake_file="mips/t-iris mips/t-slibgcc-irix"

gcc/config/mep/constraints.md

+;; Toshiba Media Processor Machine constraints
+;; Copyright (C) 2009 Free Software Foundation, Inc.
+;; Contributed by Red Hat Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.  */
+
+
+
+(define_register_constraint "a" "SP_REGS"
+  "The $sp register.")
+
+(define_register_constraint "b" "TP_REGS"
+  "The $tp register.")
+
+(define_register_constraint "c" "CONTROL_REGS"
+  "Any control register.")
+
+(define_register_constraint "d" "HILO_REGS"
+  "Either the $hi or the $lo register.")
+
+(define_register_constraint "em" "LOADABLE_CR_REGS"
+  "Coprocessor registers that can be directly loaded ($c0-$c15).")
+
+(define_register_constraint "ex" "mep_have_copro_copro_moves_p ? CR_REGS : NO_REGS"
+  "Coprocessor registers that can be moved to each other.")
+
+(define_register_constraint "er" "mep_have_core_copro_moves_p ? CR_REGS : NO_REGS"
+  "Coprocessor registers that can be moved to core registers.")
+
+(define_register_constraint "h" "HI_REGS"
+  "The $hi register.")
+
+(define_register_constraint "j" "RPC_REGS"
+  "The $rpc register.")
+
+(define_register_constraint "l" "LO_REGS"
+  "The $lo register.")
+
+(define_register_constraint "t" "TPREL_REGS"
+  "Registers which can be used in $tp-relative addressing.")
+
+(define_register_constraint "v" "GP_REGS"
+  "The $gp register.")
+
+(define_register_constraint "x" "CR_REGS"
+  "The coprocessor registers.")
+
+(define_register_constraint "y" "CCR_REGS"
+  "The coprocessor control registers.")
+
+(define_register_constraint "z" "R0_REGS"
+  "The $0 register.")
+
+(define_register_constraint "A" "USER0_REGS"
+  "User-defined register set A.")
+
+(define_register_constraint "B" "USER1_REGS"
+  "User-defined register set B.")
+
+(define_register_constraint "C" "USER2_REGS"
+  "User-defined register set C.")
+
+(define_register_constraint "D" "USER3_REGS"
+  "User-defined register set D.")
+
+
+
+(define_constraint "I"
+  "Offsets for $gp-rel addressing."
+  (and (match_code "const_int")
+       (match_test "ival >= -32768 && ival < 32768")))
+
+(define_constraint "J"
+  "Constants that can be used directly with boolean insns."
+  (and (match_code "const_int")
+       (match_test "ival >= 0 && ival < 65536")))
+
+(define_constraint "K"
+  "Constants that can be moved directly to registers."
+  (and (match_code "const_int")
+       (match_test "ival >= 0 && ival < 0x01000000")))
+
+(define_constraint "L"
+  "Small constants that can be added to registers."
+  (and (match_code "const_int")
+       (match_test "ival >= -32 && ival < 32")))
+
+(define_constraint "M"
+  "Long shift counts."
+  (and (match_code "const_int")
+       (match_test "ival >= 0 && ival < 32")))
+
+(define_constraint "N"
+  "Small constants that can be compared to registers."
+  (and (match_code "const_int")
+       (match_test "ival >= 0 && ival < 16")))
+
+(define_constraint "O"
+  "Constants that can be loaded into the top half of registers."
+  (and (match_code "const_int")
+       (match_test "!(ival & 0xffff) && ival >= -2147483647-1 && ival <= 2147483647")))
+
+(define_constraint "S"
+  "Signed 8-bit immediates."
+  (and (match_code "const_int")
+       (match_test "ival >= -128 && ival < 127")))
+
+
+
+;; This must only be used with mep_call_address_operand() as the predicate.
+(define_constraint "R"
+  "@internal
+Near symbols that can be used as addresses for CALL."
+  (not (match_code "reg")))
+
+(define_constraint "T"
+  "Symbols encoded for $tp-rel or $gp-rel addressing."
+  (ior (ior
+	(and (match_code "unspec")
+	     (match_code "symbol_ref" "a"))
+	(and (match_code "const")
+	     (and (match_code "unspec" "0")
+		  (match_code "symbol_ref" "0a"))))
+       (and (match_code "const")
+	    (and (match_code "plus" "0")
+		 (and (match_code "unspec" "00")
+		      (match_code "symbol_ref" "00a"))))))
+
+(define_constraint "U"
+  "Non-constant addresses for loading/saving coprocessor registers."
+  (and (match_code "mem")
+       (match_test "! CONSTANT_P (XEXP (op, 0))")))
+
+(define_constraint "W"
+  "The top half of a symbol's value."
+  (and (match_code "high")
+       (match_code "symbol_ref" "0")))
+
+(define_constraint "Y"
+  "A register indirect address without offset."
+  (and (match_code "mem")
+       (match_code "reg" "0")))
+
+(define_constraint "Z"
+  "Symbolic references to the control bus."
+  (and (and (match_code "mem")
+	    (match_code "symbol_ref" "0"))
+       (match_test "mep_section_tag (op) == 'c'")))

gcc/config/mep/default.h

+/* Header created by MeP-Integrator */
+#undef __section
+#define __section(_secname) __attribute__((section(#_secname)))
+#undef mep_nop
+#define mep_nop() __asm__ volatile ("nop")
+
+#pragma GCC coprocessor available $c0...$c31
+#pragma GCC coprocessor call_saved $c6...$c7
+
+#include <intrinsics.h>

gcc/config/mep/ivc2-template.h

+#undef __section
+#define __section(_secname) __attribute__((section(#_secname)))
+#undef mep_nop
+#define mep_nop() __asm__ volatile ("nop")
+
+#pragma GCC coprocessor available $c0...$c31
+#pragma GCC coprocessor call_saved $c6...$c7
+
+#include <intrinsics.h>

gcc/config/mep/mep-c5.cpu

+; Insns introduced for the MeP-c5 core
+;
+
+(dnf f-c5n4     "extended field"     (all-mep-core-isas)   16  4)
+(dnf f-c5n5     "extended field"     (all-mep-core-isas)   20  4)
+(dnf f-c5n6     "extended field"     (all-mep-core-isas)   24  4)
+(dnf f-c5n7     "extended field"     (all-mep-core-isas)   28  4)
+(dnf f-rl5      "register l c5"      (all-mep-core-isas)   20  4)
+(df  f-12s20    "extended field"     (all-mep-core-isas)   20  12  INT #f #f)
+
+(dnop rl5       "register Rl c5"     (all-mep-core-isas) h-gpr   f-rl5)
+(dnop cdisp12   "copro addend (12 bits)" (all-mep-core-isas) h-sint  f-12s20)
+
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
+     "stcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 12))
+     (c-call VOID "do_stcb" rn (and rma #xffff))
+     ((mep (unit u-use-gpr (in usereg rn))
+	   (unit u-use-gpr (in usereg rma))
+	   (unit u-exec)
+	   (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
+     "ldcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 13))
+     (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+      ((mep (unit u-use-gpr (in usereg rma))
+	    (unit u-ldcb)
+	    (unit u-exec)
+	    (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
+     "pref $cimm4,($rma)"
+     (+ MAJ_7 cimm4 rma (f-sub4 5))
+     (sequence ()
+	       (c-call VOID "check_option_dcache" pc)
+	       (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
+     "pref $cimm4,$sdisp16($rma)"
+     (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
+     (sequence ()
+	       (c-call VOID "check_option_dcache" pc)
+	       (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "casb3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
+      (sequence ()
+		(c-call VOID "do_casb3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "cash3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
+      (sequence ()
+		(c-call VOID "do_cash3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "casw3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
+      (sequence ()
+		(c-call VOID "do_casw3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+
+
+(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "sbcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+	       (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lbcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lbucp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+
+(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "shcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+	       (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lhcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lhucp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+
+(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+     "lbucpa $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (add rma cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+     "lhucpa $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (add rma (ext SI cdisp10a2))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
+     "lbucpm0 $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (mod0 cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
+     "lhucpm0 $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (mod0 cdisp10a2)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
+     "lbucpm1 $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (mod1 cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5))
+     "lhucpm1 $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (mod1 cdisp10a2)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci uci "uci" ((MACH c5) VOLATILE)
+     "uci $rn,$rm,$uimm16"
+     (+ MAJ_15 rn rm (f-sub4 2) simm16)
+     (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
+     ((mep (unit u-use-gpr (in usereg rm))
+	   (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))
+
+(dnf f-c5-rnm     "register n/m"              (all-mep-isas)    4  8)
+(dnf f-c5-rm      "register m"              (all-mep-isas)    8  4)
+(df  f-c5-16u16  "general 16-bit u-val"    (all-mep-isas) 16 16 UINT #f #f)
+
+(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+      (f-c5-rm f-c5-16u16)
+      (sequence () ; insert
+		(set (ifield f-c5-rm)    (srl (ifield f-c5-rmuimm20) 16))
+		(set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
+		)
+      (sequence () ; extract
+		(set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
+						(sll (ifield f-c5-rm) 16)))
+		)
+      )
+(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
+
+(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+      (f-c5-rnm f-c5-16u16)
+      (sequence () ; insert
+		(set (ifield f-c5-rnm)    (srl (ifield f-c5-rnmuimm24) 16))
+		(set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
+		)
+      (sequence () ; extract
+		(set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
+						(sll (ifield f-c5-rnm) 16)))
+		)
+      )
+(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
+
+(dnci dsp "dsp" ((MACH c5) VOLATILE)
+     "dsp $rn,$rm,$uimm16"
+     (+ MAJ_15 rn rm (f-sub4 0) uimm16)
+     (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
+     ((mep (unit u-use-gpr (in usereg rm))
+	   (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))
+
+(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS)
+     "dsp0 $c5rnmuimm24"
+     (+ MAJ_15 c5rnmuimm24 (f-sub4 0))
+     (c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc)
+     ((mep (unit u-exec))))
+
+(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS)
+     "dsp1 $rn,$c5rmuimm20"
+     (+ MAJ_15 rn (f-sub4 0) c5rmuimm20)
+     (set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc))
+     ((mep (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))

gcc/config/mep/mep-default.cpu

+; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
+; Copyright (C) 2001 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+; This file serves as a wrapper to bring in the core description plus
+; sample implementations of the UCI and DSP instructions.
+
+(include "mep-core.cpu")
+(include "mep-ext-cop.cpu")

gcc/config/mep/mep-ext-cop.cpu

+; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
+; Copyright (C) 2003 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+;; begin-user-isa-includes
+(include "mep-ivc2.cpu")
+;; end-user-isa-includes

gcc/config/mep/mep-lib1.asm

+/* libgcc routines for Toshiba Media Processor.
+   Copyright (C) 2001, 2002, 2005, 2009 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+  
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+  
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#define SAVEALL \
+	add3	$sp, $sp, -16*4 ; \
+	sw	$0, ($sp) ; \
+	sw	$1, 4($sp) ; \
+	sw	$2, 8($sp) ; \
+	sw	$3, 12($sp) ; \
+	sw	$4, 16($sp) ; \
+	sw	$5, 20($sp) ; \
+	sw	$6, 24($sp) ; \
+	sw	$7, 28($sp) ; \
+	sw	$8, 32($sp) ; \
+	sw	$9, 36($sp) ; \
+	sw	$10, 40($sp) ; \
+	sw	$11, 44($sp) ; \
+	sw	$12, 48($sp) ; \
+	sw	$13, 52($sp) ; \
+	sw	$14, 56($sp) ; \
+	ldc	$5, $lp	; \
+	add	$5, 3 ; \
+	mov	$6, -4 ; \
+	and	$5, $6
+
+#define RESTOREALL \
+	stc	$5, $lp ; \
+	lw	$14, 56($sp) ; \
+	lw	$13, 52($sp) ; \
+	lw	$12, 48($sp) ; \
+	lw	$11, 44($sp) ; \
+	lw	$10, 40($sp) ; \
+	lw	$9, 36($sp) ; \
+	lw	$8, 32($sp) ; \
+	lw	$7, 28($sp) ; \
+	lw	$6, 24($sp) ; \
+	lw	$5, 20($sp) ; \
+	lw	$4, 16($sp) ; \
+	lw	$3, 12($sp) ; \
+	lw	$2, 8($sp) ; \
+	lw	$1, 4($sp) ; \
+	lw	$0, ($sp) ; \
+	add3	$sp, $sp, 16*4 ; \
+	ret
+
+#ifdef L_mep_profile
+	.text
+	.global __mep_mcount
+__mep_mcount:
+	SAVEALL
+	ldc	$1, $lp
+	mov	$2, $0
+	bsr	__mep_mcount_2
+	RESTOREALL
+#endif
+
+#ifdef L_mep_bb_init_trace
+	.text
+	.global __mep_bb_init_trace_func
+__mep_bb_init_trace_func:
+	SAVEALL
+	lw	$1, ($5)
+	lw	$2, 4($5)
+	add	$5, 8
+	bsr	__bb_init_trace_func
+	RESTOREALL
+#endif
+
+#ifdef L_mep_bb_init
+	.text
+	.global __mep_bb_init_func
+__mep_bb_init_func:
+	SAVEALL
+	lw	$1, ($5)
+	add	$5, 4
+	bsr	__bb_init_func
+	RESTOREALL
+#endif
+
+#ifdef L_mep_bb_trace
+	.text
+	.global __mep_bb_trace_func
+__mep_bb_trace_func:
+	SAVEALL
+	movu	$3, __bb
+	lw	$1, ($5)
+	sw	$1, ($3)
+	lw	$2, 4($5)
+	sw	$2, 4($3)
+	add	$5, 8
+	bsr	__bb_trace_func
+	RESTOREALL
+#endif
+
+#ifdef L_mep_bb_increment
+	.text
+	.global __mep_bb_increment_func
+__mep_bb_increment_func:
+	SAVEALL
+	lw	$1, ($5)
+	lw	$0, ($1)
+	add	$0, 1
+	sw	$0, ($1)
+	add	$5, 4
+	RESTOREALL
+#endif

gcc/config/mep/mep-lib2.c

+/* libgcc routines for MeP.
+   Copyright 2001, 2002, 2009 Free Software Foundation, Inc
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+  
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+  
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+typedef		 int SItype		__attribute__ ((mode (SI)));
+typedef unsigned int USItype		__attribute__ ((mode (SI)));
+
+typedef int word_type			__attribute__ ((mode (__word__)));
+
+USItype
+__mulsi3 (USItype a, USItype b)
+{
+  USItype c = 0;
+
+  while (a != 0)
+    {
+      if (a & 1)
+	c += b;
+      a >>= 1;
+      b <<= 1;
+    }
+
+  return c;
+}
+
+
+
+USItype
+udivmodsi4(USItype num, USItype den, word_type modwanted)
+{
+  USItype bit = 1;
+  USItype res = 0;
+
+  while (den < num && bit && !(den & (1L<<31)))
+    {
+      den <<=1;
+      bit <<=1;
+    }
+  while (bit)
+    {
+      if (num >= den)
+	{
+	  num -= den;
+	  res |= bit;
+	}
+      bit >>=1;
+      den >>=1;
+    }
+  if (modwanted) return num;
+  return res;
+}
+
+
+
+SItype
+__divsi3 (SItype a, SItype b)
+{
+  word_type neg = 0;
+  SItype res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = !neg;
+    }
+
+  if (b < 0)
+    {
+      b = -b;
+      neg = !neg;
+    }
+
+  res = udivmodsi4 (a, b, 0);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+
+
+SItype
+__modsi3 (SItype a, SItype b)
+{
+  word_type neg = 0;
+  SItype res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = 1;
+    }
+
+  if (b < 0)
+    b = -b;
+
+  res = udivmodsi4 (a, b, 1);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+
+
+
+SItype
+__udivsi3 (SItype a, SItype b)
+{
+  return udivmodsi4 (a, b, 0);
+}
+
+
+
+SItype
+__umodsi3 (SItype a, SItype b)
+{
+  return udivmodsi4 (a, b, 1);
+}

gcc/config/mep/mep-pragma.c

+/* Definitions of Toshiba Media Processor
+   Copyright (C) 2001, 2002, 2003, 2005, 2006, 2007, 2009 Free
+   Software Foundation, Inc.  Contributed by Red Hat, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include <stdio.h>
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "toplev.h"
+#include "c-pragma.h"
+#include "cpplib.h"
+#include "hard-reg-set.h"
+#include "output.h"
+#include "mep-protos.h"
+#include "function.h"
+#define MAX_RECOG_OPERANDS 10
+#include "reload.h"
+#include "target.h"
+
+enum cw_which { CW_AVAILABLE, CW_CALL_SAVED };
+
+static enum cpp_ttype
+mep_pragma_lex (tree *valp)
+{
+  enum cpp_ttype t = pragma_lex (valp);
+  if (t == CPP_EOF)
+    t = CPP_PRAGMA_EOL;
+  return t;
+}
+
+static void
+mep_pragma_io_volatile (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+  /* On off.  */
+  tree val;
+  enum cpp_ttype type;
+  const char * str;
+
+  type = mep_pragma_lex (&val);
+  if (type == CPP_NAME)
+    {
+      str = IDENTIFIER_POINTER (val);
+
+      type = mep_pragma_lex (&val);
+      if (type != CPP_PRAGMA_EOL)
+	warning (0, "junk at end of #pragma io_volatile");
+
+      if (strcmp (str, "on") == 0)
+	{
+	  target_flags |= MASK_IO_VOLATILE;
+	  return;
+	}
+      if (strcmp (str, "off") == 0)
+	{
+	  target_flags &= ~ MASK_IO_VOLATILE;
+	  return;
+	}
+    }
+
+  error ("#pragma io_volatile takes only on or off");
+}
+
+static unsigned int
+parse_cr_reg (const char * str)
+{
+  unsigned int regno;
+
+  regno = decode_reg_name (str);
+  if (regno >= FIRST_PSEUDO_REGISTER)
+    return INVALID_REGNUM;
+
+  /* Verify that the regno is in CR_REGS.  */
+  if (! TEST_HARD_REG_BIT (reg_class_contents[CR_REGS], regno))
+    return INVALID_REGNUM;
+  return regno;
+}
+
+static bool
+parse_cr_set (HARD_REG_SET * set)
+{
+  tree val;
+  enum cpp_ttype type;
+  unsigned int last_regno = INVALID_REGNUM;
+  bool do_range = false;
+
+  CLEAR_HARD_REG_SET (*set);
+
+  while ((type = mep_pragma_lex (&val)) != CPP_PRAGMA_EOL)
+    {
+      if (type == CPP_COMMA)
+	{
+	  last_regno = INVALID_REGNUM;
+	  do_range = false;
+	}
+      else if (type == CPP_ELLIPSIS)
+	{
+	  if (last_regno == INVALID_REGNUM)
+	    {
+	      error ("invalid coprocessor register range");
+	      return false;
+	    }
+	  do_range = true;
+	}
+      else if (type == CPP_NAME || type == CPP_STRING)
+	{
+	  const char *str;
+	  unsigned int regno, i;
+
+	  if (TREE_CODE (val) == IDENTIFIER_NODE)
+	    str = IDENTIFIER_POINTER (val);
+  	  else if (TREE_CODE (val) == STRING_CST)
+	    str = TREE_STRING_POINTER (val);
+	  else
+	    gcc_unreachable ();
+
+	  regno = parse_cr_reg (str);
+	  if (regno == INVALID_REGNUM)
+	    {
+	      error ("invalid coprocessor register %qE", val);
+	      return false;
+	    }
+
+	  if (do_range)
+	    {
+	      if (last_regno > regno)
+		i = regno, regno = last_regno;
+	      else
+		i = last_regno;
+	      do_range = false;
+	    }
+	  else
+	    last_regno = i = regno;
+
+	  while (i <= regno)
+	    {
+	      SET_HARD_REG_BIT (*set, i);
+	      i++;
+	    }
+	}
+      else
+	{
+	  error ("malformed coprocessor register");
+	  return false;
+	}
+    }
+  return true;
+}
+
+static void
+mep_pragma_coprocessor_which (enum cw_which cw_which)
+{
+  HARD_REG_SET set;
+
+  /* Process the balance of the pragma and turn it into a hard reg set.  */
+  if (! parse_cr_set (&set))
+    return;
+
+  /* Process the collected hard reg set.  */
+  switch (cw_which)
+    {
+    case CW_AVAILABLE:
+      {
+	int i;
+	for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+	  if (TEST_HARD_REG_BIT (set, i))
+	    fixed_regs[i] = 0;
+      }
+      break;
+
+    case CW_CALL_SAVED:
+      {
+	int i;
+	for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+	  if (TEST_HARD_REG_BIT (set, i))
+	    fixed_regs[i] = call_used_regs[i] = 0;
+      }
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  /* Fix up register class hierarchy.  */
+  save_register_info ();
+  reinit_regs ();
+
+  if (cfun == 0)
+    {
+      init_dummy_function_start ();
+      init_caller_save ();
+      expand_dummy_function_end ();
+    }
+  else
+    {
+      init_caller_save ();
+    }
+}
+
+static void
+mep_pragma_coprocessor_width (void)
+{
+  tree val;
+  enum cpp_ttype type;
+  HOST_WIDE_INT i;
+
+  type = mep_pragma_lex (&val);
+  switch (type)
+    {
+    case CPP_NUMBER:
+      if (! host_integerp (val, 1))
+	break;
+      i = tree_low_cst (val, 1);
+      /* This pragma no longer has any effect.  */
+#if 0
+      if (i == 32)
+	target_flags &= ~MASK_64BIT_CR_REGS;
+      else if (i == 64)
+	target_flags |= MASK_64BIT_CR_REGS;
+      else
+	break;
+      targetm.init_builtins ();
+#else
+      if (i != 32 && i != 64)
+	break;
+#endif
+
+      type = mep_pragma_lex (&val);
+      if (type != CPP_PRAGMA_EOL)
+	warning (0, "junk at end of #pragma GCC coprocessor width");
+      return;
+
+    default:
+      break;
+    }
+
+  error ("#pragma GCC coprocessor width takes only 32 or 64");
+}
+
+static void
+mep_pragma_coprocessor_subclass (void)
+{
+  tree val;
+  enum cpp_ttype type;
+  HARD_REG_SET set;
+  int class_letter;
+  enum reg_class class;
+
+  type = mep_pragma_lex (&val);
+  if (type != CPP_CHAR)
+    goto syntax_error;
+  class_letter = tree_low_cst (val, 1);
+  if (class_letter >= 'A' && class_letter <= 'D')
+    class = class_letter - 'A' + USER0_REGS;
+  else
+    {
+      error ("#pragma GCC coprocessor subclass letter must be in [ABCD]");
+      return;
+    }
+  if (reg_class_size[class] > 0)
+    {
+      error ("#pragma GCC coprocessor subclass '%c' already defined",
+	     class_letter);
+      return;
+    }
+
+  type = mep_pragma_lex (&val);
+  if (type != CPP_EQ)
+    goto syntax_error;
+
+  if (! parse_cr_set (&set))
+    return;
+
+  /* Fix up register class hierarchy.  */
+  COPY_HARD_REG_SET (reg_class_contents[class], set);
+  init_regs ();
+  return;
+
+ syntax_error:
+  error ("malformed #pragma GCC coprocessor subclass");
+}
+
+static void
+mep_pragma_disinterrupt (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+  tree val;
+  enum cpp_ttype type;
+  int saw_one = 0;
+
+  for (;;)
+    {
+      type = mep_pragma_lex (&val);
+      if (type == CPP_COMMA)
+	continue;
+      if (type != CPP_NAME)
+	break;
+      mep_note_pragma_disinterrupt (IDENTIFIER_POINTER (val));
+      saw_one = 1;
+    }
+  if (!saw_one || type != CPP_PRAGMA_EOL)
+    {
+      error ("malformed #pragma disinterrupt");
+      return;
+    }
+}
+
+static void
+mep_pragma_coprocessor (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+  tree val;
+  enum cpp_ttype type;
+
+  type = mep_pragma_lex (&val);
+  if (type != CPP_NAME)
+    {
+      error ("malformed #pragma GCC coprocessor");
+      return;
+    }
+
+  if (!TARGET_COP)
+    error ("coprocessor not enabled");
+
+  if (strcmp (IDENTIFIER_POINTER (val), "available") == 0)
+    mep_pragma_coprocessor_which (CW_AVAILABLE);
+  else if (strcmp (IDENTIFIER_POINTER (val), "call_saved") == 0)
+    mep_pragma_coprocessor_which (CW_CALL_SAVED);
+  else if (strcmp (IDENTIFIER_POINTER (val), "width") == 0)
+    mep_pragma_coprocessor_width ();
+  else if (strcmp (IDENTIFIER_POINTER (val), "subclass") == 0)
+    mep_pragma_coprocessor_subclass ();
+  else
+    error ("unknown #pragma GCC coprocessor %E", val);
+}
+
+static void
+mep_pragma_call (cpp_reader *reader ATTRIBUTE_UNUSED)
+{
+  tree val;
+  enum cpp_ttype type;
+  int saw_one = 0;
+
+  for (;;)
+    {
+      type = mep_pragma_lex (&val);
+      if (type == CPP_COMMA)
+	continue;
+      if (type != CPP_NAME)
+	break;
+      mep_note_pragma_call (IDENTIFIER_POINTER (val));
+      saw_one = 1;
+    }
+  if (!saw_one || type != CPP_PRAGMA_EOL)
+    {
+      error ("malformed #pragma call");
+      return;
+    }
+}
+
+void
+mep_register_pragmas (void)
+{
+  c_register_pragma ("custom", "io_volatile", mep_pragma_io_volatile);
+  c_register_pragma ("GCC", "coprocessor", mep_pragma_coprocessor);
+  c_register_pragma (0, "disinterrupt", mep_pragma_disinterrupt);
+  c_register_pragma (0, "call", mep_pragma_call);
+}

gcc/config/mep/mep-protos.h

+/* Prototypes for exported functions defined in mep.c
+   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 Free
+   Software Foundation, Inc.
+   Contributed by Red Hat Inc (dj@redhat.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+extern void mep_conditional_register_usage (char *, char *);
+extern void mep_optimization_options (void);
+extern void mep_override_options (void);
+extern int mep_regno_reg_class (int);
+extern int mep_reg_class_from_constraint (int, const char *);
+extern bool mep_const_ok_for_letter_p (HOST_WIDE_INT, int);
+extern bool mep_extra_constraint (rtx, int);
+extern rtx mep_mulr_source (rtx, rtx, rtx, rtx);
+extern bool mep_reuse_lo_p (rtx, rtx, rtx, bool);
+extern bool mep_use_post_modify_p (rtx, rtx, rtx);
+extern bool mep_allow_clip (rtx, rtx, int);
+extern bool mep_bit_position_p (rtx, bool);
+extern bool mep_split_mov (rtx *, int);
+extern bool mep_vliw_mode_match (rtx);
+extern bool mep_multi_slot (rtx);
+extern bool mep_legitimate_address (enum machine_mode, rtx, int);
+extern int mep_legitimize_address (rtx *, rtx, enum machine_mode);
+#ifdef MAX_RELOADS
+extern int mep_legitimize_reload_address (rtx *, enum machine_mode, int, enum reload_type, int);
+#endif
+extern int mep_core_address_length (rtx, int);
+extern int mep_cop_address_length (rtx, int);
+extern bool mep_expand_mov (rtx *, enum machine_mode);
+extern bool mep_mov_ok (rtx *, enum machine_mode);
+extern void mep_split_wide_move (rtx *, enum machine_mode);
+#ifdef RTX_CODE
+extern bool mep_expand_setcc (rtx *);
+extern rtx mep_expand_cbranch (rtx *);
+#endif
+extern const char *mep_emit_cbranch (rtx *, int);
+extern void mep_expand_call (rtx *, int);
+extern rtx mep_find_base_term (rtx);
+extern int mep_secondary_input_reload_class (enum reg_class, enum machine_mode, rtx);
+extern int mep_secondary_output_reload_class (enum reg_class, enum machine_mode, rtx);
+extern bool mep_secondary_memory_needed (enum reg_class, enum reg_class,
+					 enum machine_mode);
+extern void mep_expand_reload (rtx *, enum machine_mode);
+extern enum reg_class mep_preferred_reload_class (rtx, enum reg_class);
+extern int mep_register_move_cost (enum machine_mode, enum reg_class, enum reg_class);
+extern void mep_init_expanders (void);
+extern rtx mep_return_addr_rtx (int);
+extern bool mep_epilogue_uses (int);
+extern int mep_elimination_offset (int, int);
+extern void mep_expand_prologue (void);
+extern void mep_expand_epilogue (void);
+extern void mep_expand_eh_return (rtx *);
+extern void mep_emit_eh_epilogue (rtx *);
+extern void mep_expand_sibcall_epilogue (void);
+extern rtx mep_return_stackadj_rtx (void);
+extern rtx mep_return_handler_rtx (void);
+extern void mep_function_profiler (FILE *);
+extern const char *mep_emit_bb_trace_ret (void);
+extern void mep_print_operand_address (FILE *, rtx);
+extern void mep_print_operand (FILE *, rtx, int);
+extern void mep_final_prescan_insn (rtx, rtx *, int);
+extern void mep_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
+extern rtx mep_function_arg (CUMULATIVE_ARGS, enum machine_mode, tree, int);
+extern void mep_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern bool mep_return_in_memory (const_tree, const_tree);
+extern rtx mep_function_value (tree, tree);
+extern rtx mep_libcall_value (enum machine_mode);
+extern void mep_asm_output_opcode (FILE *, const char *);
+extern void mep_note_pragma_disinterrupt (const char *);
+extern void mep_note_pragma_call (const char *);
+extern void mep_file_cleanups (void);
+extern const char *mep_strip_name_encoding (const char *);
+extern void mep_output_aligned_common (FILE *, tree, const char *,
+				       int, int, int);
+extern void mep_init_trampoline (rtx, rtx, rtx);
+extern void mep_emit_doloop (rtx *, int);
+extern bool mep_vliw_function_p (tree);
+extern bool mep_store_data_bypass_p (rtx, rtx);
+extern bool mep_mul_hilo_bypass_p (rtx, rtx);
+extern bool mep_ipipe_ldc_p (rtx);
+extern bool mep_emit_intrinsic (int, const rtx *);
+extern bool mep_expand_unary_intrinsic (int, rtx *);
+extern bool mep_expand_binary_intrinsic (int, int, int, int, rtx *);
+extern int mep_intrinsic_length (int);
+
+extern void mep_register_pragmas (void);
+extern int mep_section_tag (rtx);
+extern bool mep_lookup_pragma_call (const char *);
+extern bool mep_have_core_copro_moves_p;
+extern bool mep_have_copro_copro_moves_p;
+
+extern bool mep_cannot_change_mode_class (enum machine_mode, enum machine_mode,
+					  enum reg_class);
+
+extern int cgen_h_uint_6a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_7a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_8a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_6a2_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_22a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_2a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_24a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_6a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_5a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_2a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_16a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_3a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_5a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_16a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_8a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_7a2_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_6a4_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_5a8_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_4a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_10a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_sint_12a1_immediate (rtx, enum machine_mode);
+extern int cgen_h_uint_20a1_immediate (rtx, enum machine_mode);

gcc/config/mep/mep-tramp.c

+/* Trampoline support for MeP
+   Copyright (C) 2004, 2007 Free Software Foundation, Inc.
+   Contributed by Red Hat Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3 of the License, or (at your
+option) any later version.
+  
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+  
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+/*
+  7a0a		ldc $10,$pc
+  c0ae000a	lw $0,10($10)
+  caae000e	lw $10,14($10)
+  10ae		jmp $10
+  00000000	static chain
+  00000000	function address
+*/
+
+static inline int
+cache_config_register(void) {
+  int rv;
+  asm ("ldc\t%0, $ccfg" : "=r" (rv));
+  return rv;
+}
+
+#define ICACHE_SIZE ((cache_config_register() >> 16) & 0x7f)
+#define DCACHE_SIZE (cache_config_register() & 0x7f)
+
+#define ICACHE_DATA_BASE 0x00300000
+#define ICACHE_TAG_BASE  0x00310000
+#define DCACHE_DATA_BASE 0x00320000
+#define DCACHE_TAG_BASE  0x00330000
+
+static inline void
+flush_dcache (int addr)
+{
+  asm volatile ("cache\t0, (%0)" : : "r" (addr));
+}
+
+void
+__mep_trampoline_helper (unsigned long *tramp,
+			 int function_address,
+			 int static_chain);
+
+void
+__mep_trampoline_helper (unsigned long *tramp,
+			 int function_address,
+			 int static_chain)
+{
+  int dsize, isize;
+
+#ifdef __LITTLE_ENDIAN__
+  tramp[0] = 0xc0ae7a0a;
+  tramp[1] = 0xcaae000a;
+  tramp[2] = 0x10ae000e;
+#else
+  tramp[0] = 0x7a0ac0ae;
+  tramp[1] = 0x000acaae;
+  tramp[2] = 0x000e10ae;
+#endif
+  tramp[3] = static_chain;
+  tramp[4] = function_address;
+
+  dsize = DCACHE_SIZE;
+  isize = ICACHE_SIZE;
+
+  if (dsize)
+    {
+      flush_dcache ((int)tramp);
+      flush_dcache ((int)tramp+16);
+    }
+
+  if (isize)
+    {
+      int imask = (isize * 1024) - 1;
+      int tmask = ~imask;
+      unsigned int i;
+      volatile unsigned int *tags;
+
+      imask &= 0xffe0;
+
+      for (i=(unsigned int)tramp; i<(unsigned int)tramp+20; i+=16)
+	{
+	  tags = (unsigned int *)(ICACHE_TAG_BASE + (i & imask));
+	  if ((*tags & tmask) == (i & tmask))
+	    *tags &= ~1;
+	}
+    }
+}

gcc/config/mep/mep.cpu

+(include "mep-default.cpu")

gcc/config/mep/mep.opt

+; Target specific command line options for the MEP port of the compiler.
+; Copyright (C) 2005, 2007, 2009 Free Software Foundation, Inc.
+; Contributed by Red Hat Inc.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+; 
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+; for more details.
+; 
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3.  If not see
+; <http://www.gnu.org/licenses/>.  */
+
+mabsdiff
+Target Mask(OPT_ABSDIFF)
+Enable absolute difference instructions
+
+mall-opts
+Target RejectNegative
+Enable all optional instructions
+
+maverage
+Target Mask(OPT_AVERAGE)
+Enable average instructions
+
+mbased=
+Target Joined Var(mep_based_cutoff) RejectNegative UInteger Init(0)
+Variables this size and smaller go in the based section. (default 0)
+
+mbitops
+Target Mask(OPT_BITOPS)
+Enable bit manipulation instructions
+
+mc=
+Target Joined Var(mep_const_section) RejectNegative
+Section to put all const variables in (tiny, near, far) (no default)
+
+mclip
+Target Mask(OPT_CLIP)
+Enable clip instructions
+
+mconfig=
+Target Joined Var(mep_config_string) RejectNegative
+Configuration name
+
+mcop
+Target Mask(COP)
+Enable MeP Coprocessor
+
+mcop32
+Target Mask(COP) MaskExists RejectNegative
+Enable MeP Coprocessor with 32-bit registers
+
+mcop64
+Target Mask(64BIT_CR_REGS) RejectNegative
+Enable MeP Coprocessor with 64-bit registers
+
+mivc2
+Target Mask(IVC2) RejectNegative
+Enable IVC2 scheduling
+
+mdc
+Target Mask(DC) RejectNegative
+Const variables default to the near section
+
+mdebug
+Target Disabled Undocumented
+
+mdiv
+Target Mask(OPT_DIV)
+Enable 32-bit divide instructions
+
+meb
+Target InverseMask(LITTLE_ENDIAN) RejectNegative
+Use big-endian byte order
+
+mel
+Target Mask(LITTLE_ENDIAN) RejectNegative
+Use little-endian byte order
+
+mfar
+Target RejectNegative
+Enable -ml, -mtf, and -mc=far
+
+mio-volatile
+Target Mask(IO_VOLATILE) 
+__io vars are volatile by default
+
+ml
+Target Mask(L) RejectNegative
+All variables default to the far section
+
+mleadz
+Target Mask(OPT_LEADZ)
+Enable leading zero instructions
+
+mlibrary
+Target Mask(LIBRARY) RejectNegative Undocumented
+
+mm
+Target Mask(M) RejectNegative
+All variables default to the near section
+
+mminmax
+Target Mask(OPT_MINMAX)
+Enable min/max instructions
+
+mmult
+Target Mask(OPT_MULT)
+Enable 32-bit multiply instructions
+
+mno-opts
+Target RejectNegative
+Disable all optional instructions
+
+mrand-tpgp
+Target Mask(RAND_TPGP) RejectNegative Undocumented
+
+mrepeat
+Target Mask(OPT_REPEAT)
+Allow gcc to use the repeat/erepeat instructions
+
+ms
+Target Mask(S) RejectNegative
+All variables default to the tiny section
+
+msatur
+Target Mask(OPT_SATUR)
+Enable saturation instructions
+
+msdram
+Target 
+Use sdram version of runtime
+
+msim
+Target RejectNegative
+Use simulator runtime
+
+msimnovec
+Target RejectNegative
+Use simulator runtime without vectors
+
+mtf
+Target Mask(TF) RejectNegative
+All functions default to the far section
+
+mtiny=
+Target Joined Var(mep_tiny_cutoff) RejectNegative UInteger Init(4)
+Variables this size and smaller go in the tiny section. (default 4)
+
+mvl32
+Target InverseMask(OPT_VL64) Undocumented RejectNegative
+
+mvl64
+Target Mask(OPT_VL64) Undocumented RejectNegative
+
+mvliw
+Target Mask(VLIW) Undocumented

gcc/config/mep/predicates.md

+;; Toshiba Media Processor Machine predicates
+;; Copyright (C) 2009 Free Software Foundation, Inc.
+;; Contributed by Red Hat Inc.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.  */
+
+;; (define_predicate "cgen_h_uint_7a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_6a2_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_22a4_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_2a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_24a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_6a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_5a4_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_2a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_16a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_3a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_5a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_16a1_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_sint_5a8_immediate"
+;;    (match_code "const_int"))
+;; (define_predicate "cgen_h_uint_4a1_immediate"
+;;    (match_code "const_int"))
+
+(define_predicate "cgen_h_sint_7a2_immediate"
+   (match_code "const_int")
+   { int i = INTVAL (op);
+     return ((i & 1) == 0 && i >= -128 && i < 128);
+   })
+
+(define_predicate "cgen_h_sint_6a4_immediate"
+   (match_code "const_int")
+   { int i = INTVAL (op);
+     return ((i & 3) == 0 && i >= -256 && i < 256);
+   })
+
+;; This is used below, to simplify things.
+(define_predicate "mep_subreg_operand"
+  (ior
+   (and (and (and (match_code "subreg")
+		  (match_code "reg" "0"))
+	     (match_test "REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER"))
+	(match_test "!(reload_completed || reload_in_progress)"))
+   (and (match_code "reg")
+	(match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+
+(define_predicate "symbolic_operand"
+  (match_code "const,symbol_ref,label_ref"))
+
+(define_predicate "mep_farsym_operand"
+  (and (match_code "const,symbol_ref")
+       (match_test "mep_section_tag (op) == 'f'")))
+
+(define_predicate "mep_nearsym_operand"
+  (and (match_code "const,symbol_ref,label_ref")
+       (match_test "mep_section_tag (op) != 'f'")))
+
+(define_predicate "mep_movdest_operand"
+  (and (match_test "mep_section_tag (op) != 'f'")
+       (match_operand 0 "nonimmediate_operand")))
+
+(define_predicate "mep_r0_15_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "GR_REGNO_P (REGNO (op))"))))
+
+(define_predicate "mep_r0_operand"
+  (and (match_code "reg")
+       (ior (match_test "REGNO (op) == 0")
+	    (match_test "!(reload_completed || reload_in_progress)
+		         && REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+
+(define_predicate "mep_hi_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == HI_REGNO"))))
+
+(define_predicate "mep_lo_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == LO_REGNO"))))
+
+(define_predicate "mep_tp_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == TP_REGNO"))))
+
+(define_predicate "mep_gp_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == GP_REGNO"))))
+
+(define_predicate "mep_sp_operand"
+  (match_test "op == stack_pointer_rtx"))
+
+(define_predicate "mep_tprel_operand"
+  (ior (match_operand 0 "mep_subreg_operand")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) < 8"))))
+
+(define_predicate "mep_call_address_operand"
+  (and (match_test "mep_section_tag (op) != 'f'")
+       (and (ior (not (match_code "symbol_ref"))
+		 (match_test "mep_section_tag (DECL_RTL (cfun->decl)) != 'f'
+			      && !mep_lookup_pragma_call (XSTR (op, 0))"))
+	    (match_code "symbol_ref,reg"))))
+
+(define_predicate "mep_Y_operand"
+  (and (match_code "mem")
+       (match_code "reg" "0")))
+
+(define_predicate "mep_imm4_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
+
+(define_predicate "mep_reg_or_imm4_operand"
+  (ior (match_code "reg")
+       (and (match_code "const_int")
+	    (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))))
+
+(define_predicate "mep_imm7a4_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) >= 0 && INTVAL (op) < 128 && INTVAL (op) % 4 == 0")))
+
+(define_predicate "mep_slad_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
+
+(define_predicate "mep_add_operand"
+  (ior (and (match_code "const")
+	    (and (match_operand 0 "symbolic_operand")
+		 (and (match_test "mep_section_tag(op) == 'b' || mep_section_tag(op) == 't'")
+		      (ior (match_code "unspec" "0")
+			   (and (match_code "plus" "0")
+				(match_code "unspec" "00"))))))
+       (match_code "const_int,reg")))
+
+;; Return true if OP is an integer in the range 0..7 inclusive.
+;; On the MeP-h1, shifts by such constants execute in a single stage
+;; and shifts by larger values execute in two.
+(define_predicate "mep_single_shift_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
+
+;; Return true if OP is an operation that can be performed using bsetm,
+;; bclrm or bnotm.  The possibilities are:
+
+;; bsetm: (ior X Y), Y has one bit set
+;; bclrm: (and X Y), Y has one bit clear
+;; bnotm: (xor X Y), Y has one bit set.
+(define_predicate "mep_bit_operator"
+  (and (match_code "and,ior,xor")
+       (match_test "mep_bit_position_p (XEXP (op, 1), GET_CODE (op) != AND)")))
+
+(define_predicate "mep_reload_operand"
+  (ior (and (match_code "reg")
+	    (match_test "!ANY_CONTROL_REGNO_P (REGNO (op))"))
+       (and (match_code "mem,symbol_ref")
+	    (match_test "mep_section_tag (op) != 'f'"))))

gcc/config/mep/t-mep

+# -*- makefile -*-
+# GCC makefile fragment for MeP
+# Copyright (C) 2001, 2002, 2003, 2005, 2007, 2009
+# Free Software Foundation, Inc.
+# Contributed by Red Hat Inc
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+# Force genpreds to be rebuilt in case MeP-Integrator changed the predicates
+
+GTM_H = tm.h $(tm_file_list) $(srcdir)/config/mep/mep-intrin.h
+
+# Use -O0 instead of -O2 so we don't get complex relocations
+
+CRTSTUFF_CFLAGS = -O0 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+  -finhibit-size-directive -fno-inline-functions -fno-exceptions \
+  -fno-zero-initialized-in-bss -fno-unit-at-a-time
+
+TCFLAGS = -mlibrary
+
+mep-pragma.o: $(srcdir)/config/mep/mep-pragma.c $(CONFIG_H) $(SYSTEM_H) \
+	coretypes.h $(TM_H) $(TREE_H) $(RTL_H) toplev.h c-pragma.h \
+	$(CPPLIB_H) hard-reg-set.h output.h $(srcdir)/config/mep/mep-protos.h \
+	function.h insn-config.h reload.h $(TARGET_H)
+	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+
+# profiling support
+
+LIB1ASMSRC = mep/mep-lib1.asm
+
+LIB1ASMFUNCS = _mep_profile \
+	       _mep_bb_init_trace \
+	       _mep_bb_init \
+	       _mep_bb_trace \
+	       _mep_bb_increment
+
+# multiply and divide routines
+
+LIB2FUNCS_EXTRA = \
+	$(srcdir)/config/mep/mep-lib2.c \
+	$(srcdir)/config/mep/mep-tramp.c
+
+# floating point emulation libraries
+
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT'				> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c			>> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+MULTILIB_OPTIONS = mel mall-opts mfar
+MULTILIB_DIRNAMES = el allopt far
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+
+MD_INCLUDES = \
+	$(srcdir)/config/mep/intrinsics.md \
+	$(srcdir)/config/mep/predicates.md \
+	$(srcdir)/config/mep/constraints.md
+
+mep.o : $(srcdir)/config/mep/mep-intrin.h
+
+# begin-isas
+MEP_CORE = ext_core1
+MEP_COPRO = ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64
+# end-isas
+
+# To use this, you must have cgen and cgen/cpu in the same source tree as
+# gcc.
+cgen-maint :
+	S=`cd $(srcdir); pwd`; \
+	cd $$S/config/mep && \
+	guile -s $$S/../cgen/cgen-intrinsics.scm \
+		-s $$S/../cgen \
+		$(CGENFLAGS) \
+		-a $$S/../cgen/cpu/mep.cpu \
+		-m mep,c5 \
+		-i mep,$(MEP_CORE),$(MEP_COPRO) \
+		-K mep,$(MEP_CORE),$(MEP_COPRO) \
+		-M intrinsics.md \
+		-N mep-intrin.h \
+		-P intrinsics.h
+
+# start-extra-headers
+EXTRA_HEADERS = $(srcdir)/config/mep/intrinsics.h \
+	$(srcdir)/config/mep/default.h
+# end-extra-headers

gcc/recog.c

@@ -738,6 +738,17 @@ validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object,
     simplify_while_replacing (loc, to, object, op0_mode);
 }
 
+/* Try replacing every occurrence of FROM in subexpression LOC of INSN
+   with TO.  After all changes have been made, validate by seeing
+   if INSN is still valid.  */
+
+int
+validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc)
+{
+  validate_replace_rtx_1 (loc, from, to, insn, true);
+  return apply_change_group ();
+}
+
 /* Try replacing every occurrence of FROM in INSN with TO.  After all
    changes have been made, validate by seeing if INSN is still valid.  */
 

gcc/recog.h

@@ -86,6 +86,7 @@ extern int constrain_operands (int);
 extern int constrain_operands_cached (int);
 extern int memory_address_p (enum machine_mode, rtx);
 extern int strict_memory_address_p (enum machine_mode, rtx);
+extern int validate_replace_rtx_subexp (rtx, rtx, rtx, rtx *);
 extern int validate_replace_rtx (rtx, rtx, rtx);
 extern int validate_replace_rtx_part (rtx, rtx, rtx *, rtx);
 extern int validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx);

gcc/testsuite/ChangeLog

+2009-06-23  DJ Delorie  <dj@redhat.com>
+
+	Add MeP port.
+	* lib/target-supports.exp: Add mep support (no profiling).
+
 2009-06-23  Steve Ellcey  <sje@cup.hp.com>
 
 	PR testsuite/39297

gcc/testsuite/lib/target-supports.exp

@@ -498,6 +498,7 @@ proc check_profiling_available { test_what } {
 	     || [istarget m32c-*-elf]
 	     || [istarget m68k-*-elf]
 	     || [istarget m68k-*-uclinux*]
+	     || [istarget mep-*-elf]
 	     || [istarget mips*-*-elf*]
 	     || [istarget moxie-*-elf*]
 	     || [istarget xstormy16-*]

libgcc/ChangeLog

+2009-06-23  DJ Delorie  <dj@redhat.com>
+
+	Add MeP port.
+	* config.host: Add mep support.
+
 2009-06-22  Kai Tietz  <kai.tietz@onevision.com>
 
 	* config.host: Add i386/${host_address}/t-fprules-softfp and

libgcc/config.host

@@ -102,6 +102,8 @@ m32r*-*-*)
         ;;
 m68k-*-*)
 	;;
+mep*-*-*)
+	;;
 mips*-*-*)
 	cpu_type=mips
 	;;
@@ -553,6 +555,8 @@ am33_2.0-*-linux*)
 	;;
 m32c-*-elf*|m32c-*-rtems*)
  	;;
+mep*-*-*)
+	;;
 *)
 	echo "*** Configuration ${host} not supported" 1>&2
 	exit 1

libstdc++-v3/ChangeLog

+2009-06-23  DJ Delorie  <dj@redhat.com>
+
+	Add MeP port.
+	* configure.host: Add mep support.
+
 2009-06-23  Benjamin Kosnik  <bkoz@redhat.com>
 
 	* doc/doxygen/user.cfg.in (PREDEFINED): Add _GLIBCXX_ATOMIC_BUILTINS_*.

libstdc++-v3/configure.host

@@ -103,6 +103,10 @@ case "${host_cpu}" in
   hppa*)
     try_cpu=hppa
     ;;
+  mep*)
+    EXTRA_CXX_FLAGS=-mm
+    try_cpu=generic
+    ;;
   mips*)
     try_cpu=mips
     ;;