re PR middle-end/18008 (Duplicate mask on bitfield insertion)

        PR middle-end/18008
        * c-decl.c (finish_struct): Set DECL_MODE after resetting a
        field's type.
        * expmed.c (store_fixed_bit_field): Create a paradoxical subreg
        if we don't need the bits above those present in the current mode.
        * expr.c (store_field): Strip conversions to odd-bit-sized types
        if the destination field width matches.

From-SVN: r94290

gcc/ChangeLog

+2005-01-26  Richard Henderson  <rth@redhat.com>
+
+	PR middle-end/18008
+	* c-decl.c (finish_struct): Set DECL_MODE after resetting a
+	field's type.
+	* expmed.c (store_fixed_bit_field): Create a paradoxical subreg
+	if we don't need the bits above those present in the current mode.
+	* expr.c (store_field): Strip conversions to odd-bit-sized types
+	if the destination field width matches.
+
 2005-01-26  Richard Sandiford  <rsandifo@redhat.com>
 
 	* config/mips/iris6.h (ENDFILE_SPEC): Don't link in irix-csr.o if
@@ -33,6 +43,7 @@
 	* configure.ac: Check for a TLS capable gas.
 
 	* configure: Regenerate.
+
 2005-01-26  Richard Henderson  <rth@redhat.com>
 
 	PR middle-end/18008

gcc/c-decl.c

@@ -5301,8 +5301,11 @@ finish_struct (tree t, tree fieldlist, tree attributes)
 	    = tree_low_cst (DECL_INITIAL (*fieldlistp), 1);
 	  tree type = TREE_TYPE (*fieldlistp);
 	  if (width != TYPE_PRECISION (type))
-	    TREE_TYPE (*fieldlistp)
-	      = build_nonstandard_integer_type (width, TYPE_UNSIGNED (type));
+	    {
+	      TREE_TYPE (*fieldlistp)
+	        = build_nonstandard_integer_type (width, TYPE_UNSIGNED (type));
+	      DECL_MODE (*fieldlistp) = TYPE_MODE (TREE_TYPE (*fieldlistp));
+	    }
 	  DECL_INITIAL (*fieldlistp) = 0;
 	}
       else

gcc/expmed.c

@@ -878,7 +878,7 @@ store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
       if (GET_MODE (value) != mode)
 	{
 	  if ((REG_P (value) || GET_CODE (value) == SUBREG)
-	      && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
+	      && GET_MODE_SIZE (GET_MODE (value)) <= bitsize)
 	    value = gen_lowpart (mode, value);
 	  else
 	    value = convert_to_mode (mode, value, 1);

gcc/expr.c

@@ -5215,7 +5215,21 @@ store_field (rtx target, HOST_WIDE_INT bitsize, HOST_WIDE_INT bitpos,
 	  && TREE_CODE (TYPE_SIZE (TREE_TYPE (exp))) == INTEGER_CST
 	  && compare_tree_int (TYPE_SIZE (TREE_TYPE (exp)), bitsize) != 0))
     {
-      rtx temp = expand_expr (exp, NULL_RTX, VOIDmode, 0);
+      rtx temp;
+
+      /* If EXP is a NOP_EXPR of precision less than its mode, then that
+	 implies a mask operation.  If the precision is the same size as
+	 the field we're storing into, that mask is redundant.  This is
+	 particularly common with bit field assignments generated by the
+	 C front end.  */
+      if (TREE_CODE (exp) == NOP_EXPR
+	  && INTEGRAL_TYPE_P (TREE_TYPE (exp))
+	  && (TYPE_PRECISION (TREE_TYPE (exp))
+	      < GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (exp))))
+	  && bitsize == TYPE_PRECISION (TREE_TYPE (exp)))
+	exp = TREE_OPERAND (exp, 0);
+
+      temp = expand_expr (exp, NULL_RTX, VOIDmode, 0);
 
       /* If BITSIZE is narrower than the size of the type of EXP
 	 we will be narrowing TEMP.  Normally, what's wanted are the