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Commit 78d310c2 by J"orn Rennecke Committed by Joern Rennecke
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crt1.asm: Fix #ifdef indent. 

gcc:

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>

	* config/sh/crt1.asm: Fix #ifdef indent.

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>
	Merged from STMicroelectronics sources:
	2006-10-06  Andrew Stubbs  <andrew.stubbs@st.com>
	  * config/sh/crt1.asm (vbr_600): Add missing #if.
	2006-08-03  J"orn Rennecke  <joern.rennecke@st.com>
	  * sh.opt (mfused-madd): New option.
	  * sh.md (mac_media, macsf3): Make conditional on TARGET_FMAC.
	2006-07-04  Andrew Stubbs  <andrew.stubbs@st.com>
	  * config/sh/crt1.asm (vbr_start): Move to new section .test.vbr.
	  Remove pointless handler at VBR+0.
	  (vbr_200, vbr_300, vbr_500): Remove pointless handler.
	  (vbr_600): Save and restore mach and macl, fpul and fpscr and fr0 to
	  fr7. Make sure the timer handler is called with the correct FPU
	  precision setting, according to the ABI.
	2006-06-14  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/sh.opt (m2a-single, m2a-single-only): Fix Condition.
	  * config/sh/sh.h (SUPPORT_SH2A_NOFPU): Fix condition.
	  (SUPPORT_SH2A_SINGLE_ONLY, SUPPORT_SH2A_SINGLE_ONLY): Likewise.
	2006-06-09  J"orn Rennecke <joern.rennecke@st.com>
	  * sh.md (cmpgeusi_t): Change into define_insn_and_split.  Accept
	  zero as second operand.
	2006-04-28  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
	  Fixed some bugs related to negative values, in particular -0
	  and overflow at -0x80000000.
	  * config/sh/divcost-analysis: Added sh4-300 figures.
	2006-04-27  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/t-sh (MULTILIB_MATCHES): Add -m4-300* / -m4-340 options.
	2006-04-26  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/t-sh (OPT_EXTRA_PARTS): Add libgcc-4-300.a.
	  ($(T)div_table-4-300.o, $(T)libgcc-4-300.a): New rules.
	  * config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
	New files.
	  * config/sh/embed-elf.h (LIBGCC_SPEC): Use -lgcc-4-300 for -m4-300* /
	  -m4-340.
	2006-04-24  J"orn Rennecke <joern.rennecke@st.com>
	  SH4-300 scheduling description & fixes to SH4-[12]00 description:
	  * sh.md: New instruction types: fstore, movi8, fpscr_toggle, gp_mac,
	  mac_mem, mem_mac, dfp_mul, fp_cmp.
	  (insn_class, dfp_comp, any_fp_comp): Update.
	  (push_fpul, movsf_ie, fpu_switch, toggle_sz, toggle_pr): Update type.
	  (cmpgtsf_t, "cmpeqsf_t, cmpgtsf_t_i4, cmpeqsf_t_i4): Likewise.
	  (muldf3_i): Likewise.
	  (movsi_i): Split rI08 alternative into two separate alternatives.
	  Update type.
	  (movsi_ie, movsi_i_lowpart): Likewise.
	  (movqi_i): Split ri alternative into two separate alternatives.
	  Update type.
	  * sh1.md (sh1_load_store, sh1_fp): Update.
	  * sh4.md (sh4_store, sh4_mac_gp, fp_arith, fp_double_arith): Update.
	  (mac_mem, sh4_fpscr_toggle): New insn_reservations.
	  * sh4a.md (sh4a_mov, sh4a_load, sh4a_store, sh4a_fp_arith): Update.
	  (sh4a_fp_double_arith): Likewise.
	  * sh4-300.md: New file.
	  * sh.c (sh_handle_option): Handle m4-300* options.
	  (sh_adjust_cost): Fix latency of auto-increments.
	  Handle SH4-300 differently than other SH4s.  Check for new insn types.
	  * sh.h (OVERRIDE_OPTIONS): Initilize sh_branch_cost if it has not
	  been set by an option.
	  * sh.opt (m4-300, m4-100-nofpu, m4-200-nofpu): New options.
	  (m4-300-nofpu, -m4-340, m4-300-single, m4-300-single-only): Likewise.
	  (mbranch-cost=): Likewise.
	  * superh.h (STARTFILE_SPEC): Take -m4-340 into account.

	  * sh.md (mulsf3): Remove special expansion code.
	  (mulsf3_ie): Now a define_insn_and_split.
	  (macsf3): Allow for TARGET_SH4.

	  * sh.md (cbranchsi4, cbranchdi4, cbranchdi4_i): New patterns.
	  * sh.c (prepare_cbranch_operands, expand_cbranchsi4): New functions.
	  (expand_cbranchdi4): Likewise.
	  (sh_rtx_costs): Give lower cost for certain CONST_INT values and for
	  CONST_DOUBLE if the outer code is COMPARE.
	  * sh.h (OPTIMIZATION_OPTIONS): If not optimizing for size, set
	  TARGET_CBRANCHDI4 and TARGET_EXPAND_CBRANCHDI4.
	  (OVERRIDE_OPTIONS): For TARGET_SHMEDIA, clear TARGET_CBRANCHDI4.
	  (LEGITIMATE_CONSTANT_P): Also allow DImode and VOIDmode CONST_DOUBLEs.
	  Remove redundant fp_{zero,one}_operand checks.
	  * sh.opt (mcbranchdi, mexpand-cbranchdi, mcmpeqdi): New options.
	  * sh-protos.h (prepare_cbranch_operands, expand_cbranchsi4): Declare.
	  (expand_cbranchdi4): Likewise.
	2006-04-20  J"orn Rennecke <joern.rennecke@st.com>
	  * sh.h (LOCAL_ALIGNMENT): Use DATA_ALIGNMENT.

gcc/testsuite:

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>

	* testsuite/gcc.c-torture/execute/arith-rand-ll.c:
	Also test for bogus rest sign.

From-SVN: r118458
parent 47c07d96
Showing with 356 additions and 120 deletions
gcc/ChangeLog
2006-11-03 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/crt1.asm: Fix #ifdef indent.
2006-11-03 J"orn Rennecke <joern.rennecke@st.com>
Merged from STMicroelectronics sources:
2006-10-06 Andrew Stubbs <andrew.stubbs@st.com>
* config/sh/crt1.asm (vbr_600): Add missing #if.
2006-08-03 J"orn Rennecke <joern.rennecke@st.com>
* sh.opt (mfused-madd): New option.
* sh.md (mac_media, macsf3): Make conditional on TARGET_FMAC.
2006-07-04 Andrew Stubbs <andrew.stubbs@st.com>
* config/sh/crt1.asm (vbr_start): Move to new section .test.vbr.
Remove pointless handler at VBR+0.
(vbr_200, vbr_300, vbr_500): Remove pointless handler.
(vbr_600): Save and restore mach and macl, fpul and fpscr and fr0 to
fr7. Make sure the timer handler is called with the correct FPU
precision setting, according to the ABI.
2006-06-14 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.opt (m2a-single, m2a-single-only): Fix Condition.
* config/sh/sh.h (SUPPORT_SH2A_NOFPU): Fix condition.
(SUPPORT_SH2A_SINGLE_ONLY, SUPPORT_SH2A_SINGLE_ONLY): Likewise.
2006-06-09 J"orn Rennecke <joern.rennecke@st.com>
* sh.md (cmpgeusi_t): Change into define_insn_and_split. Accept
zero as second operand.
2006-04-28 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
Fixed some bugs related to negative values, in particular -0
and overflow at -0x80000000.
* config/sh/divcost-analysis: Added sh4-300 figures.
2006-04-27 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/t-sh (MULTILIB_MATCHES): Add -m4-300* / -m4-340 options.
2006-04-26 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/t-sh (OPT_EXTRA_PARTS): Add libgcc-4-300.a.
($(T)div_table-4-300.o, $(T)libgcc-4-300.a): New rules.
* config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
New files.
* config/sh/embed-elf.h (LIBGCC_SPEC): Use -lgcc-4-300 for -m4-300* /
-m4-340.
2006-04-24 J"orn Rennecke <joern.rennecke@st.com>
SH4-300 scheduling description & fixes to SH4-[12]00 description:
* sh.md: New instruction types: fstore, movi8, fpscr_toggle, gp_mac,
mac_mem, mem_mac, dfp_mul, fp_cmp.
(insn_class, dfp_comp, any_fp_comp): Update.
(push_fpul, movsf_ie, fpu_switch, toggle_sz, toggle_pr): Update type.
(cmpgtsf_t, "cmpeqsf_t, cmpgtsf_t_i4, cmpeqsf_t_i4): Likewise.
(muldf3_i): Likewise.
(movsi_i): Split rI08 alternative into two separate alternatives.
Update type.
(movsi_ie, movsi_i_lowpart): Likewise.
(movqi_i): Split ri alternative into two separate alternatives.
Update type.
* sh1.md (sh1_load_store, sh1_fp): Update.
* sh4.md (sh4_store, sh4_mac_gp, fp_arith, fp_double_arith): Update.
(mac_mem, sh4_fpscr_toggle): New insn_reservations.
* sh4a.md (sh4a_mov, sh4a_load, sh4a_store, sh4a_fp_arith): Update.
(sh4a_fp_double_arith): Likewise.
* sh4-300.md: New file.
* sh.c (sh_handle_option): Handle m4-300* options.
(sh_adjust_cost): Fix latency of auto-increments.
Handle SH4-300 differently than other SH4s. Check for new insn types.
* sh.h (OVERRIDE_OPTIONS): Initilize sh_branch_cost if it has not
been set by an option.
* sh.opt (m4-300, m4-100-nofpu, m4-200-nofpu): New options.
(m4-300-nofpu, -m4-340, m4-300-single, m4-300-single-only): Likewise.
(mbranch-cost=): Likewise.
* superh.h (STARTFILE_SPEC): Take -m4-340 into account.
* sh.md (mulsf3): Remove special expansion code.
(mulsf3_ie): Now a define_insn_and_split.
(macsf3): Allow for TARGET_SH4.
* sh.md (cbranchsi4, cbranchdi4, cbranchdi4_i): New patterns.
* sh.c (prepare_cbranch_operands, expand_cbranchsi4): New functions.
(expand_cbranchdi4): Likewise.
(sh_rtx_costs): Give lower cost for certain CONST_INT values and for
CONST_DOUBLE if the outer code is COMPARE.
* sh.h (OPTIMIZATION_OPTIONS): If not optimizing for size, set
TARGET_CBRANCHDI4 and TARGET_EXPAND_CBRANCHDI4.
(OVERRIDE_OPTIONS): For TARGET_SHMEDIA, clear TARGET_CBRANCHDI4.
(LEGITIMATE_CONSTANT_P): Also allow DImode and VOIDmode CONST_DOUBLEs.
Remove redundant fp_{zero,one}_operand checks.
* sh.opt (mcbranchdi, mexpand-cbranchdi, mcmpeqdi): New options.
* sh-protos.h (prepare_cbranch_operands, expand_cbranchsi4): Declare.
(expand_cbranchdi4): Likewise.
2006-04-20 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (LOCAL_ALIGNMENT): Use DATA_ALIGNMENT.
2006-11-02 Andrew Pinski <andrew_pinski@playstation.sony.com> 2006-11-02 Andrew Pinski <andrew_pinski@playstation.sony.com>
* doc/md.texi (RS6000 constraints): Document H, Z, a, t, and W * doc/md.texi (RS6000 constraints): Document H, Z, a, t, and W
......
gcc/config/sh/crt1.asm
/* Copyright (C) 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. /* Copyright (C) 2000, 2001, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
This file was pretty much copied from newlib. This file was pretty much copied from newlib.
This file is part of GCC. This file is part of GCC.
...@@ -894,25 +895,12 @@ ___main: ...@@ -894,25 +895,12 @@ ___main:
nop nop
#ifdef VBR_SETUP #ifdef VBR_SETUP
! Exception handlers ! Exception handlers
.balign 256 .section .text.vbr, "ax"
vbr_start: vbr_start:
mov.l 2f, r0 ! load the old vbr setting (if any)
mov.l @r0, r0
cmp/eq #0, r0
bf 1f
! no previous vbr - jump to own generic handler
bra handler
nop
1: ! there was a previous handler - chain them
jmp @r0
nop
.balign 4
2:
.long old_vbr
.balign 256 .org 0x100
vbr_100: vbr_100:
#ifdef PROFILE #ifdef PROFILE
! Note on register usage. ! Note on register usage.
! we use r0..r3 as scratch in this code. If we are here due to a trapa for profiling ! we use r0..r3 as scratch in this code. If we are here due to a trapa for profiling
! then this is OK as we are just before executing any function code. ! then this is OK as we are just before executing any function code.
...@@ -1017,50 +1005,7 @@ handler_100: ...@@ -1017,50 +1005,7 @@ handler_100:
2: 2:
.long old_vbr .long old_vbr
.balign 256 .org 0x400
vbr_200:
mov.l 2f, r0 ! load the old vbr setting (if any)
mov.l @r0, r0
cmp/eq #0, r0
bf 1f
! no previous vbr - jump to own generic handler
bra handler
nop
1: ! there was a previous handler - chain them
add #0x7f, r0 ! 0x7f
add #0x7f, r0 ! 0xfe
add #0x7f, r0 ! 0x17d
add #0x7f, r0 ! 0x1fc
add #0x4, r0 ! add 0x200 without corrupting another register
jmp @r0
nop
.balign 4
2:
.long old_vbr
.balign 256
vbr_300:
mov.l 2f, r0 ! load the old vbr setting (if any)
mov.l @r0, r0
cmp/eq #0, r0
bf 1f
! no previous vbr - jump to own generic handler
bra handler
nop
1: ! there was a previous handler - chain them
rotcr r0
rotcr r0
add #0x7f, r0 ! 0x1fc
add #0x41, r0 ! 0x300
rotcl r0
rotcl r0 ! Add 0x300 without corrupting another register
jmp @r0
nop
.balign 4
2:
.long old_vbr
.balign 256
vbr_400: ! Should be at vbr+0x400 vbr_400: ! Should be at vbr+0x400
mov.l 2f, r0 ! load the old vbr setting (if any) mov.l 2f, r0 ! load the old vbr setting (if any)
mov.l @r0, r0 mov.l @r0, r0
...@@ -1103,28 +1048,7 @@ handler: ...@@ -1103,28 +1048,7 @@ handler:
jmp @r2 jmp @r2
nop nop
.balign 256 .org 0x600
vbr_500:
mov.l 2f, r0 ! load the old vbr setting (if any)
mov.l @r0, r0
cmp/eq #0, r0
! no previous vbr - jump to own generic handler
bt handler
! there was a previous handler - chain them
rotcr r0
rotcr r0
add #0x7f, r0 ! 0x1fc
add #0x7f, r0 ! 0x3f8
add #0x42, r0 ! 0x500
rotcl r0
rotcl r0 ! Add 0x500 without corrupting another register
jmp @r0
nop
.balign 4
2:
.long old_vbr
.balign 256
vbr_600: vbr_600:
#ifdef PROFILE #ifdef PROFILE
! Should be at vbr+0x600 ! Should be at vbr+0x600
...@@ -1140,11 +1064,48 @@ vbr_600: ...@@ -1140,11 +1064,48 @@ vbr_600:
mov.l r6,@-r15 mov.l r6,@-r15
mov.l r7,@-r15 mov.l r7,@-r15
sts.l pr,@-r15 sts.l pr,@-r15
sts.l mach,@-r15
sts.l macl,@-r15
#if defined(__SH_FPU_ANY__)
! Save fpul and fpscr, save fr0-fr7 in 64 bit mode
! and set the pervading precision for the timer_handler
mov #0,r0
sts.l fpul,@-r15
sts.l fpscr,@-r15
lds r0,fpscr ! Clear fpscr
fmov fr0,@-r15
fmov fr1,@-r15
fmov fr2,@-r15
fmov fr3,@-r15
mov.l pervading_precision_k,r0
fmov fr4,@-r15
fmov fr5,@-r15
mov.l @r0,r0
fmov fr6,@-r15
fmov fr7,@-r15
lds r0,fpscr
#endif /* __SH_FPU_ANY__ */
! Pass interrupted pc to timer_handler as first parameter (r4). ! Pass interrupted pc to timer_handler as first parameter (r4).
stc spc, r4 stc spc, r4
mov.l timer_handler_k, r0 mov.l timer_handler_k, r0
jsr @r0 jsr @r0
nop nop
#if defined(__SH_FPU_ANY__)
mov #0,r0
lds r0,fpscr ! Clear the fpscr
fmov @r15+,fr7
fmov @r15+,fr6
fmov @r15+,fr5
fmov @r15+,fr4
fmov @r15+,fr3
fmov @r15+,fr2
fmov @r15+,fr1
fmov @r15+,fr0
lds.l @r15+,fpscr
lds.l @r15+,fpul
#endif /* __SH_FPU_ANY__ */
lds.l @r15+,macl
lds.l @r15+,mach
lds.l @r15+,pr lds.l @r15+,pr
mov.l @r15+,r7 mov.l @r15+,r7
mov.l @r15+,r6 mov.l @r15+,r6
...@@ -1157,6 +1118,13 @@ vbr_600: ...@@ -1157,6 +1118,13 @@ vbr_600:
stc sgr, r15 ! Restore r15, destroyed by this sequence. stc sgr, r15 ! Restore r15, destroyed by this sequence.
rte rte
nop nop
#if defined(__SH_FPU_ANY__)
.balign 4
pervading_precision_k:
#define CONCAT1(A,B) A##B
#define CONCAT(A,B) CONCAT1(A,B)
.long CONCAT(__USER_LABEL_PREFIX__,__fpscr_values)+4
#endif
#else #else
mov.l 2f, r0 ! Load the old vbr setting (if any). mov.l 2f, r0 ! Load the old vbr setting (if any).
mov.l @r0, r0 mov.l @r0, r0
......
gcc/config/sh/divcost-analysis
...@@ -38,12 +38,17 @@ div_r8_neg -> div_r8_neg_end: 18 ...@@ -38,12 +38,17 @@ div_r8_neg -> div_r8_neg_end: 18
div_le128_neg -> div_by_1_neg: 4 div_le128_neg -> div_by_1_neg: 4
div_le128_neg -> rts 18 div_le128_neg -> rts 18
absolute divisor range: sh4-200 absolute divisor range:
1 [2..128] [129..64K) [64K..|divident|/256] >=64K,>|divident/256| 1 [2..128] [129..64K) [64K..|divident|/256] >=64K,>|divident/256|
udiv 18 22 38 32 30 udiv 18 22 38 32 30
sdiv pos: 20 24 41 35 32 sdiv pos: 20 24 41 35 32
sdiv neg: 15 25 42 36 33 sdiv neg: 15 25 42 36 33
sh4-300 absolute divisor range:
8 bit 16 bit 24 bit > 24 bit
udiv 15 35 28 25
sdiv 14 36 34 31
fp-based: fp-based:
......
gcc/config/sh/divtab-sh4-300.c 0 → 100644
/* Copyright (C) 2004, 2006 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
In addition to the permissions in the GNU General Public License, the
Free Software Foundation gives you unlimited permission to link the
compiled version of this file into combinations with other programs,
and to distribute those combinations without any restriction coming
from the use of this file. (The General Public License restrictions
do apply in other respects; for example, they cover modification of
the file, and distribution when not linked into a combine
executable.)
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
/* Calculate division table for ST40-300 integer division
Contributed by Joern Rennecke
joern.rennecke@st.com */
#include <stdio.h>
#include <math.h>
int
main ()
{
int i, j;
double q, r, err, max_err = 0, max_s_err = 0;
puts("/* This table has been generated by divtab-sh4.c. */");
puts ("\t.balign 4");
for (i = -128; i < 128; i++)
{
int n = 0;
if (i == 0)
{
/* output some dummy number for 1/0. */
puts ("LOCAL(div_table_clz):\n\t.byte\t0");
continue;
}
for (j = i < 0 ? -i : i; j < 128; j += j)
n++;
printf ("\t.byte\t%d\n", n - 7);
}
puts("\
/* 1/-128 .. 1/127, normalized. There is an implicit leading 1 in bit 32,\n\
or in bit 33 for powers of two. */\n\
.balign 4");
for (i = -128; i < 128; i++)
{
if (i == 0)
{
puts ("LOCAL(div_table_inv):\n\t.long\t0x0");
continue;
}
j = i < 0 ? -i : i;
while (j < 64)
j += j;
q = 4.*(1<<30)*128/j;
r = ceil (q);
printf ("\t.long\t0x%X\n", (unsigned) r);
err = r - q;
if (err > max_err)
max_err = err;
err = err * j / 128;
if (err > max_s_err)
max_s_err = err;
}
printf ("\t/* maximum error: %f scaled: %f*/\n", max_err, max_s_err);
exit (0);
}
gcc/config/sh/embed-elf.h
...@@ -32,6 +32,7 @@ Boston, MA 02110-1301, USA. */ ...@@ -32,6 +32,7 @@ Boston, MA 02110-1301, USA. */
#define LIBGCC_SPEC "%{!shared: \ #define LIBGCC_SPEC "%{!shared: \
%{m4-100*:-lic_invalidate_array_4-100} \ %{m4-100*:-lic_invalidate_array_4-100} \
%{m4-200*:-lic_invalidate_array_4-200} \ %{m4-200*:-lic_invalidate_array_4-200} \
%{m4-300*|-m4-340:-lic_invalidate_array_4a %{!Os: -lgcc-4-300}} \
%{m4a*:-lic_invalidate_array_4a}} \ %{m4a*:-lic_invalidate_array_4a}} \
%{Os: -lgcc-Os-4-200} \ %{Os: -lgcc-Os-4-200} \
-lgcc \ -lgcc \
......
gcc/config/sh/sh-protos.h
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH. /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003, Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003,
2004, 2005 2004, 2005, 2006
Free Software Foundation, Inc. Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com). Contributed by Steve Chamberlain (sac@cygnus.com).
Improved by Jim Wilson (wilson@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com).
...@@ -69,6 +69,10 @@ extern void print_operand (FILE *, rtx, int); ...@@ -69,6 +69,10 @@ extern void print_operand (FILE *, rtx, int);
extern void output_pic_addr_const (FILE *, rtx); extern void output_pic_addr_const (FILE *, rtx);
extern int expand_block_move (rtx *); extern int expand_block_move (rtx *);
extern int prepare_move_operands (rtx[], enum machine_mode mode); extern int prepare_move_operands (rtx[], enum machine_mode mode);
extern enum rtx_code prepare_cbranch_operands (rtx *, enum machine_mode mode,
enum rtx_code comparison);
extern void expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int);
extern bool expand_cbranchdi4 (rtx *operands, enum rtx_code comparison);
extern void from_compare (rtx *, int); extern void from_compare (rtx *, int);
extern int shift_insns_rtx (rtx); extern int shift_insns_rtx (rtx);
extern void gen_ashift (int, int, rtx); extern void gen_ashift (int, int, rtx);
......
gcc/config/sh/sh.h
...@@ -274,6 +274,7 @@ do { \ ...@@ -274,6 +274,7 @@ do { \
#endif #endif
#if SUPPORT_SH2 #if SUPPORT_SH2
#define SUPPORT_SH3 1 #define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
#endif #endif
#if SUPPORT_SH3 #if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1 #define SUPPORT_SH4_NOFPU 1
...@@ -281,16 +282,17 @@ do { \ ...@@ -281,16 +282,17 @@ do { \
#if SUPPORT_SH4_NOFPU #if SUPPORT_SH4_NOFPU
#define SUPPORT_SH4A_NOFPU 1 #define SUPPORT_SH4A_NOFPU 1
#define SUPPORT_SH4AL 1 #define SUPPORT_SH4AL 1
#define SUPPORT_SH2A_NOFPU 1
#endif #endif
#if SUPPORT_SH2E #if SUPPORT_SH2E
#define SUPPORT_SH3E 1 #define SUPPORT_SH3E 1
#define SUPPORT_SH2A_SINGLE_ONLY 1
#endif #endif
#if SUPPORT_SH3E #if SUPPORT_SH3E
#define SUPPORT_SH4_SINGLE_ONLY 1 #define SUPPORT_SH4_SINGLE_ONLY 1
#endif
#if SUPPORT_SH4_SINGLE_ONLY
#define SUPPORT_SH4A_SINGLE_ONLY 1 #define SUPPORT_SH4A_SINGLE_ONLY 1
#define SUPPORT_SH2A_SINGLE_ONLY 1
#endif #endif
#if SUPPORT_SH4 #if SUPPORT_SH4
...@@ -469,6 +471,11 @@ do { \ ...@@ -469,6 +471,11 @@ do { \
target_flags |= MASK_SMALLCODE; \ target_flags |= MASK_SMALLCODE; \
sh_div_str = SH_DIV_STR_FOR_SIZE ; \ sh_div_str = SH_DIV_STR_FOR_SIZE ; \
} \ } \
else \
{ \
TARGET_CBRANCHDI4 = 1; \
TARGET_EXPAND_CBRANCHDI4 = 1; \
} \
/* We can't meaningfully test TARGET_SHMEDIA here, because -m options \ /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
haven't been parsed yet, hence we'd read only the default. \ haven't been parsed yet, hence we'd read only the default. \
sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \ sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
...@@ -608,6 +615,7 @@ do { \ ...@@ -608,6 +615,7 @@ do { \
else \ else \
sh_div_strategy = SH_DIV_INV; \ sh_div_strategy = SH_DIV_INV; \
} \ } \
TARGET_CBRANCHDI4 = 0; \
} \ } \
/* -fprofile-arcs needs a working libgcov . In unified tree \ /* -fprofile-arcs needs a working libgcov . In unified tree \
configurations with newlib, this requires to configure with \ configurations with newlib, this requires to configure with \
...@@ -668,6 +676,9 @@ do { \ ...@@ -668,6 +676,9 @@ do { \
sh_divsi3_libfunc = "__sdivsi3_1"; \ sh_divsi3_libfunc = "__sdivsi3_1"; \
else \ else \
sh_divsi3_libfunc = "__sdivsi3"; \ sh_divsi3_libfunc = "__sdivsi3"; \
if (sh_branch_cost == -1) \
sh_branch_cost \
= TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
if (TARGET_FMOVD) \ if (TARGET_FMOVD) \
reg_class_from_letter['e' - 'a'] = NO_REGS; \ reg_class_from_letter['e' - 'a'] = NO_REGS; \
\ \
...@@ -844,7 +855,7 @@ do { \ ...@@ -844,7 +855,7 @@ do { \
((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
: (unsigned) ALIGN) : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
/* Make arrays of chars word-aligned for the same reasons. */ /* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \ #define DATA_ALIGNMENT(TYPE, ALIGN) \
...@@ -2288,6 +2299,7 @@ struct sh_args { ...@@ -2288,6 +2299,7 @@ struct sh_args {
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
/* Nonzero if the constant value X is a legitimate general operand. */ /* Nonzero if the constant value X is a legitimate general operand. */
/* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
#define LEGITIMATE_CONSTANT_P(X) \ #define LEGITIMATE_CONSTANT_P(X) \
(TARGET_SHMEDIA \ (TARGET_SHMEDIA \
...@@ -2298,7 +2310,7 @@ struct sh_args { ...@@ -2298,7 +2310,7 @@ struct sh_args {
|| TARGET_SHMEDIA64) \ || TARGET_SHMEDIA64) \
: (GET_CODE (X) != CONST_DOUBLE \ : (GET_CODE (X) != CONST_DOUBLE \
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
|| (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X))))) || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class. and check its validity for a certain class.
......
gcc/config/sh/sh.opt
...@@ -57,11 +57,11 @@ Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) ...@@ -57,11 +57,11 @@ Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
Generate SH2a FPU-less code Generate SH2a FPU-less code
m2a-single m2a-single
Target RejectNegative Condition (SUPPORT_SH2A_SINGLE) Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
Generate default single-precision SH2a code Generate default single-precision SH2a code
m2a-single-only m2a-single-only
Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY) Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
Generate only single-precision SH2a code Generate only single-precision SH2a code
m2e m2e
...@@ -88,10 +88,33 @@ m4-200 ...@@ -88,10 +88,33 @@ m4-200
Target RejectNegative Condition(SUPPORT_SH4) Target RejectNegative Condition(SUPPORT_SH4)
Generate SH4-200 code Generate SH4-200 code
;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
;; pipeline - irrespective of ABI.
m4-300
Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
Generate SH4-300 code
m4-nofpu m4-nofpu
Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
Generate SH4 FPU-less code Generate SH4 FPU-less code
m4-100-nofpu
Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
Generate SH4-100 FPU-less code
m4-200-nofpu
Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
Generate SH4-200 FPU-less code
m4-300-nofpu
Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
Generate SH4-300 FPU-less code
m4-340
Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
Generate code for SH4 340 series (MMU/FPU-less)
;; passes -isa=sh4-nommu-nofpu to the assembler.
m4-400 m4-400
Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
Generate code for SH4 400 series (MMU/FPU-less) Generate code for SH4 400 series (MMU/FPU-less)
...@@ -114,6 +137,10 @@ m4-200-single ...@@ -114,6 +137,10 @@ m4-200-single
Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
Generate default single-precision SH4-200 code Generate default single-precision SH4-200 code
m4-300-single
Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
Generate default single-precision SH4-300 code
m4-single-only m4-single-only
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
Generate only single-precision SH4 code Generate only single-precision SH4 code
...@@ -126,6 +153,10 @@ m4-200-single-only ...@@ -126,6 +153,10 @@ m4-200-single-only
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
Generate only single-precision SH4-200 code Generate only single-precision SH4-200 code
m4-300-single-only
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
Generate only single-precision SH4-300 code
m4a m4a
Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
Generate SH4a code Generate SH4a code
...@@ -182,6 +213,22 @@ mbigtable ...@@ -182,6 +213,22 @@ mbigtable
Target Report RejectNegative Mask(BIGTABLE) Target Report RejectNegative Mask(BIGTABLE)
Generate 32-bit offsets in switch tables Generate 32-bit offsets in switch tables
mbranch-cost=
Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
Cost to assume for a branch insn
mcbranchdi
Target Var(TARGET_CBRANCHDI4)
Enable cbranchdi4 pattern
mexpand-cbranchdi
Target Var(TARGET_EXPAND_CBRANCHDI4)
Expand cbranchdi4 pattern early into separate comparisons and branches.
mcmpeqdi
Target Var(TARGET_CMPEQDI_T)
Emit cmpeqdi_t pattern even when -mcbranchdi and -mexpand-cbranchdi are in effect.
mcut2-workaround mcut2-workaround
Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
Enable SH5 cut2 workaround Enable SH5 cut2 workaround
...@@ -192,7 +239,7 @@ Align doubles at 64-bit boundaries ...@@ -192,7 +239,7 @@ Align doubles at 64-bit boundaries
mdiv= mdiv=
Target RejectNegative Joined Var(sh_div_str) Init("") Target RejectNegative Joined Var(sh_div_str) Init("")
Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp call-div1 call-fp call-table Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
mdivsi3_libfunc= mdivsi3_libfunc=
Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
...@@ -201,6 +248,10 @@ Specify name for 32 bit signed division function ...@@ -201,6 +248,10 @@ Specify name for 32 bit signed division function
mfmovd mfmovd
Target RejectNegative Mask(FMOVD) Undocumented Target RejectNegative Mask(FMOVD) Undocumented
mfused-madd
Target Var(TARGET_FMAC)
Enable the use of the fused floating point multiply-accumulate operation
mgettrcost= mgettrcost=
Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
Cost to assume for gettr insn Cost to assume for gettr insn
......
gcc/config/sh/sh1.md
;; DFA scheduling description for Renesas / SuperH SH. ;; DFA scheduling description for Renesas / SuperH SH.
;; Copyright (C) 2004 Free Software Foundation, Inc. ;; Copyright (C) 2004, 2006 Free Software Foundation, Inc.
;; This file is part of GCC. ;; This file is part of GCC.
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
(define_insn_reservation "sh1_load_store" 2 (define_insn_reservation "sh1_load_store" 2
(and (eq_attr "pipe_model" "sh1") (and (eq_attr "pipe_model" "sh1")
(eq_attr "type" "load,pcload,pload,store,pstore")) (eq_attr "type" "load,pcload,pload,mem_mac,store,fstore,pstore,mac_mem"))
"sh1memory*2") "sh1memory*2")
(define_insn_reservation "sh1_arith3" 3 (define_insn_reservation "sh1_arith3" 3
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
(define_insn_reservation "sh1_fp" 2 (define_insn_reservation "sh1_fp" 2
(and (eq_attr "pipe_model" "sh1") (and (eq_attr "pipe_model" "sh1")
(eq_attr "type" "fp,fmove")) (eq_attr "type" "fp,fpscr_toggle,fp_cmp,fmove"))
"sh1fp") "sh1fp")
(define_insn_reservation "sh1_fdiv" 13 (define_insn_reservation "sh1_fdiv" 13
......
gcc/config/sh/sh4.md
;; DFA scheduling description for SH4. ;; DFA scheduling description for SH4.
;; Copyright (C) 2004 Free Software Foundation, Inc. ;; Copyright (C) 2004, 2006 Free Software Foundation, Inc.
;; This file is part of GCC. ;; This file is part of GCC.
...@@ -209,9 +209,14 @@ ...@@ -209,9 +209,14 @@
(define_insn_reservation "sh4_store" 1 (define_insn_reservation "sh4_store" 1
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "store")) (eq_attr "type" "store,fstore"))
"issue+load_store,nothing,memory") "issue+load_store,nothing,memory")
(define_insn_reservation "mac_mem" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mac_mem"))
"d_lock,nothing,memory")
;; Load Store instructions. ;; Load Store instructions.
;; Group: LS ;; Group: LS
;; Latency: 1 ;; Latency: 1
...@@ -372,35 +377,42 @@ ...@@ -372,35 +377,42 @@
;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W) ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
;; Group: CO ;; Group: CO
;; Latency: 4 / 4 ;; Latency: 4 / 4
;; Issue Rate: 1 ;; Issue Rate: 2
(define_insn_reservation "multi" 4 (define_insn_reservation "multi" 4
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "smpy,dmpy")) (eq_attr "type" "smpy,dmpy"))
"d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2") "d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2")
;; Fixed STS from MACL / MACH ;; Fixed STS from, and LDS to MACL / MACH
;; Group: CO ;; Group: CO
;; Latency: 3 ;; Latency: 3
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "sh4_mac_gp" 3 (define_insn_reservation "sh4_mac_gp" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mac_gp")) (eq_attr "type" "mac_gp,gp_mac,mem_mac"))
"d_lock") "d_lock")
;; Single precision floating point computation FCMP/EQ, ;; Single precision floating point computation FCMP/EQ,
;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG
;; Group: FE ;; Group: FE
;; Latency: 3/4 ;; Latency: 3/4
;; Issue Rate: 1 ;; Issue Rate: 1
(define_insn_reservation "fp_arith" 3 (define_insn_reservation "fp_arith" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fp")) (eq_attr "type" "fp,fp_cmp"))
"issue,F01,F2") "issue,F01,F2")
;; We don't model the resource usage of this exactly because that would
;; introduce a bogus latency.
(define_insn_reservation "sh4_fpscr_toggle" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fpscr_toggle"))
"issue")
(define_insn_reservation "fp_arith_ftrc" 3 (define_insn_reservation "fp_arith_ftrc" 3
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "ftrc_s")) (eq_attr "type" "ftrc_s"))
...@@ -437,7 +449,7 @@ ...@@ -437,7 +449,7 @@
(define_insn_reservation "fp_double_arith" 8 (define_insn_reservation "fp_double_arith" 8
(and (eq_attr "pipe_model" "sh4") (and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_arith")) (eq_attr "type" "dfp_arith,dfp_mul"))
"issue,F01,F1+F2,fpu*4,F2") "issue,F01,F1+F2,fpu*4,F2")
;; Double-precision FCMP (FCMP/EQ,FCMP/GT) ;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
......
gcc/config/sh/sh4a.md
;; Scheduling description for Renesas SH4a ;; Scheduling description for Renesas SH4a
;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. ;; Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
;; ;;
;; This file is part of GCC. ;; This file is part of GCC.
;; ;;
...@@ -98,9 +98,11 @@ ...@@ -98,9 +98,11 @@
;; MOV ;; MOV
;; Group: MT ;; Group: MT
;; Latency: 0 ;; Latency: 0
;; ??? not sure if movi8 belongs here, but that's where it was
;; effectively before.
(define_insn_reservation "sh4a_mov" 0 (define_insn_reservation "sh4a_mov" 0
(and (eq_attr "cpu" "sh4a") (and (eq_attr "cpu" "sh4a")
(eq_attr "type" "move")) (eq_attr "type" "move,movi8,gp_mac"))
"ID_or") "ID_or")
;; Load ;; Load
...@@ -108,7 +110,7 @@ ...@@ -108,7 +110,7 @@
;; Latency: 3 ;; Latency: 3
(define_insn_reservation "sh4a_load" 3 (define_insn_reservation "sh4a_load" 3
(and (eq_attr "cpu" "sh4a") (and (eq_attr "cpu" "sh4a")
(eq_attr "type" "load,pcload")) (eq_attr "type" "load,pcload,mem_mac"))
"sh4a_ls+sh4a_memory") "sh4a_ls+sh4a_memory")
(define_insn_reservation "sh4a_load_si" 3 (define_insn_reservation "sh4a_load_si" 3
...@@ -121,7 +123,7 @@ ...@@ -121,7 +123,7 @@
;; Latency: 0 ;; Latency: 0
(define_insn_reservation "sh4a_store" 0 (define_insn_reservation "sh4a_store" 0
(and (eq_attr "cpu" "sh4a") (and (eq_attr "cpu" "sh4a")
(eq_attr "type" "store")) (eq_attr "type" "store,fstore,mac_mem"))
"sh4a_ls+sh4a_memory") "sh4a_ls+sh4a_memory")
;; CWB TYPE ;; CWB TYPE
...@@ -177,7 +179,7 @@ ...@@ -177,7 +179,7 @@
;; Latency: 3 ;; Latency: 3
(define_insn_reservation "sh4a_fp_arith" 3 (define_insn_reservation "sh4a_fp_arith" 3
(and (eq_attr "cpu" "sh4a") (and (eq_attr "cpu" "sh4a")
(eq_attr "type" "fp")) (eq_attr "type" "fp,fp_cmp,fpscr_toggle"))
"ID_or,sh4a_fex") "ID_or,sh4a_fex")
(define_insn_reservation "sh4a_fp_arith_ftrc" 3 (define_insn_reservation "sh4a_fp_arith_ftrc" 3
...@@ -207,7 +209,7 @@ ...@@ -207,7 +209,7 @@
;; Latency: 5 ;; Latency: 5
(define_insn_reservation "sh4a_fp_double_arith" 5 (define_insn_reservation "sh4a_fp_double_arith" 5
(and (eq_attr "cpu" "sh4a") (and (eq_attr "cpu" "sh4a")
(eq_attr "type" "dfp_arith")) (eq_attr "type" "dfp_arith,dfp_mul"))
"ID_or,sh4a_fex*3") "ID_or,sh4a_fex*3")
;; Double precision FDIV/SQRT ;; Double precision FDIV/SQRT
......
gcc/config/sh/superh.h
...@@ -75,17 +75,17 @@ Boston, MA 02110-1301, USA. */ ...@@ -75,17 +75,17 @@ Boston, MA 02110-1301, USA. */
on newlib and provide the runtime support */ on newlib and provide the runtime support */
#undef SUBTARGET_CPP_SPEC #undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC \ #define SUBTARGET_CPP_SPEC \
"-D__EMBEDDED_CROSS__ %{m4-100*:-D__SH4_100__} %{m4-200*:-D__SH4_200__} %{m4-400:-D__SH4_400__} %{m4-500:-D__SH4_500__} \ "-D__EMBEDDED_CROSS__ %{m4-100*:-D__SH4_100__} %{m4-200*:-D__SH4_200__} %{m4-300*:-D__SH4_300__} %{m4-340:-D__SH4_340__} %{m4-400:-D__SH4_400__} %{m4-500:-D__SH4_500__} \
%(cppruntime)" %(cppruntime)"
/* Override the SUBTARGET_ASM_SPEC to add the runtime support */ /* Override the SUBTARGET_ASM_SPEC to add the runtime support */
#undef SUBTARGET_ASM_SPEC #undef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC "%{m4-100*|m4-200*:-isa=sh4} %{m4-400:-isa=sh4-nommu-nofpu} %{m4-500:-isa=sh4-nofpu} %(asruntime)" #define SUBTARGET_ASM_SPEC "%{m4-100*|m4-200*:-isa=sh4} %{m4-400|m4-340:-isa=sh4-nommu-nofpu} %{m4-500:-isa=sh4-nofpu} %(asruntime)"
/* Override the SUBTARGET_ASM_RELAX_SPEC so it doesn't interfere with the /* Override the SUBTARGET_ASM_RELAX_SPEC so it doesn't interfere with the
runtime support by adding -isa=sh4 in the wrong place. */ runtime support by adding -isa=sh4 in the wrong place. */
#undef SUBTARGET_ASM_RELAX_SPEC #undef SUBTARGET_ASM_RELAX_SPEC
#define SUBTARGET_ASM_RELAX_SPEC "%{!m4-100*:%{!m4-200*:%{!m4-400:%{!m4-500:-isa=sh4}}}}" #define SUBTARGET_ASM_RELAX_SPEC "%{!m4-100*:%{!m4-200*:%{!m4-300*:%{!m4-340:%{!m4-400:%{!m4-500:-isa=sh4}}}}}}"
/* Create the CC1_SPEC to add the runtime support */ /* Create the CC1_SPEC to add the runtime support */
#undef CC1_SPEC #undef CC1_SPEC
...@@ -102,7 +102,7 @@ Boston, MA 02110-1301, USA. */ ...@@ -102,7 +102,7 @@ Boston, MA 02110-1301, USA. */
/* Override STARTFILE_SPEC to add profiling and MMU support. */ /* Override STARTFILE_SPEC to add profiling and MMU support. */
#undef STARTFILE_SPEC #undef STARTFILE_SPEC
#define STARTFILE_SPEC \ #define STARTFILE_SPEC \
"%{!shared: %{!m4-400*: %{pg:gcrt1-mmu.o%s}%{!pg:crt1-mmu.o%s}}} \ "%{!shared: %{!m4-400*:%{!m4-340*: %{pg:gcrt1-mmu.o%s}%{!pg:crt1-mmu.o%s}}}} \
%{!shared: %{m4-400*: %{pg:gcrt1.o%s}%{!pg:crt1.o%s}}} \ %{!shared: %{m4-340*|m4-400*: %{pg:gcrt1.o%s}%{!pg:crt1.o%s}}} \
crti.o%s \ crti.o%s \
%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
gcc/config/sh/t-sh
...@@ -38,11 +38,12 @@ MULTILIB_DIRNAMES= ...@@ -38,11 +38,12 @@ MULTILIB_DIRNAMES=
# is why sh2a and sh2a-single need their own multilibs. # is why sh2a and sh2a-single need their own multilibs.
MULTILIB_MATCHES = $(shell \ MULTILIB_MATCHES = $(shell \
multilibs="$(MULTILIB_OPTIONS)" ; \ multilibs="$(MULTILIB_OPTIONS)" ; \
for abi in m1,m2,m3,m4-nofpu,m4-400,m4-500,m4al,m4a-nofpu m1,m2,m2a-nofpu \ for abi in m1,m2,m3,m4-nofpu,m4-100-nofpu,m4-200-nofpu,m4-400,m4-500,m4-340,m4-300-nofpu,m4al,m4a-nofpu \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4a-single-only \ m1,m2,m2a-nofpu \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2e,m2a-single-only \ m2e,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4a-single \ m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
m4,m4-100,m4-200,m4a \ m4,m4-100,m4-200,m4-300,m4a \
m5-32media,m5-compact,m5-32media \ m5-32media,m5-compact,m5-32media \
m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
subst= ; \ subst= ; \
...@@ -76,7 +77,7 @@ gt-sh.h : s-gtype ; @true ...@@ -76,7 +77,7 @@ gt-sh.h : s-gtype ; @true
IC_EXTRA_PARTS= libic_invalidate_array_4-100.a libic_invalidate_array_4-200.a \ IC_EXTRA_PARTS= libic_invalidate_array_4-100.a libic_invalidate_array_4-200.a \
libic_invalidate_array_4a.a libic_invalidate_array_4a.a
OPT_EXTRA_PARTS= libgcc-Os-4-200.a OPT_EXTRA_PARTS= libgcc-Os-4-200.a libgcc-4-300.a
EXTRA_MULTILIB_PARTS= $(IC_EXTRA_PARTS) $(OPT_EXTRA_PARTS) EXTRA_MULTILIB_PARTS= $(IC_EXTRA_PARTS) $(OPT_EXTRA_PARTS)
$(T)ic_invalidate_array_4-100.o: $(srcdir)/config/sh/lib1funcs.asm $(GCC_PASSES) $(T)ic_invalidate_array_4-100.o: $(srcdir)/config/sh/lib1funcs.asm $(GCC_PASSES)
...@@ -104,6 +105,12 @@ OBJS_Os_4_200=$(T)sdivsi3_i4i-Os-4-200.o $(T)udivsi3_i4i-Os-4-200.o $(T)unwind-d ...@@ -104,6 +105,12 @@ OBJS_Os_4_200=$(T)sdivsi3_i4i-Os-4-200.o $(T)udivsi3_i4i-Os-4-200.o $(T)unwind-d
$(T)libgcc-Os-4-200.a: $(OBJS_Os_4_200) $(GCC_PASSES) $(T)libgcc-Os-4-200.a: $(OBJS_Os_4_200) $(GCC_PASSES)
$(AR_CREATE_FOR_TARGET) $@ $(OBJS_Os_4_200) $(AR_CREATE_FOR_TARGET) $@ $(OBJS_Os_4_200)
$(T)div_table-4-300.o: $(srcdir)/config/sh/lib1funcs-4-300.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $@ -DL_div_table -x assembler-with-cpp $<
$(T)libgcc-4-300.a: $(T)div_table-4-300.o $(GCC_PASSES)
$(AR_CREATE_FOR_TARGET) $@ $(T)div_table-4-300.o
# Local Variables: # Local Variables:
# mode: Makefile # mode: Makefile
# End: # End:
gcc/testsuite/ChangeLog
2006-11-03 J"orn Rennecke <joern.rennecke@st.com>
* testsuite/gcc.c-torture/execute/arith-rand-ll.c:
Also test for bogus rest sign.
2006-11-03 Francois-Xavier Coudert <coudert@clipper.ens.fr> 2006-11-03 Francois-Xavier Coudert <coudert@clipper.ens.fr>
PR libfortran/27895 PR libfortran/27895
gcc/testsuite/gcc.c-torture/execute/arith-rand-ll.c
...@@ -79,7 +79,7 @@ main () ...@@ -79,7 +79,7 @@ main ()
continue; continue;
r1 = xx / yy; r1 = xx / yy;
r2 = xx % yy; r2 = xx % yy;
if (ABS (r2) >= (unsigned int) ABS (yy) || (signed int) (r1 * yy + r2) != xx) if (ABS (r2) >= (unsigned int) ABS (yy) || (signed int) (r1 * yy + r2) != xx || ((xx < 0) != (r2 < 0) && r2))
abort (); abort ();
} }
{ unsigned short xx = x, yy = y, r1, r2; { unsigned short xx = x, yy = y, r1, r2;
......
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