Commit 77cea46e by Igor Zamyatin Committed by Kirill Yukhin

invoke.texi (core-avx2): Document.

        * doc/invoke.texi (core-avx2): Document.
        (slm): Likewise.
        (atom): Updated with MOVBE.

From-SVN: r199943
parent 888f0920
2013-06-11 Igor Zamyatin <igor.zamyatin@intel.com>
* doc/invoke.texi (core-avx2): Document.
(slm): Likewise.
(atom): Updated with MOVBE.
2013-06-11 Richard Biener <rguenther@suse.de> 2013-06-11 Richard Biener <rguenther@suse.de>
* collect2.c (main): Do not redirect ld stdout/stderr when * collect2.c (main): Do not redirect ld stdout/stderr when
......
...@@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, ...@@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction
set support. set support.
@item core-avx2
Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2
and F16C instruction set support.
@item atom @item atom
Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support. instruction set support.
@item slm
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1 and SSE4.2 instruction set support.
@item k6 @item k6
AMD K6 CPU with MMX instruction set support. AMD K6 CPU with MMX instruction set support.
......
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